AES/UNMASKED Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: `2bd4e85`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	59.606us	1	1	100.00
V1	smoke	aes_smoke	4.000s	197.434us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	62.803us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	140.115us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	5.000s	597.941us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	94.343us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	64.147us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	140.115us	20	20	100.00
		aes_csr_aliasing	3.000s	94.343us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	197.434us	50	50	100.00
		aes_config_error	3.000s	73.205us	50	50	100.00
		aes_stress	4.000s	119.857us	50	50	100.00
V2	key_length	aes_smoke	4.000s	197.434us	50	50	100.00
		aes_config_error	3.000s	73.205us	50	50	100.00
		aes_stress	4.000s	119.857us	50	50	100.00
V2	back2back	aes_stress	4.000s	119.857us	50	50	100.00
		aes_b2b	7.000s	136.634us	50	50	100.00
V2	backpressure	aes_stress	4.000s	119.857us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	197.434us	50	50	100.00
		aes_config_error	3.000s	73.205us	50	50	100.00
		aes_stress	4.000s	119.857us	50	50	100.00
		aes_alert_reset	4.000s	184.708us	50	50	100.00
V2	failure_test	aes_man_cfg_err	3.000s	138.380us	50	50	100.00
		aes_config_error	3.000s	73.205us	50	50	100.00
		aes_alert_reset	4.000s	184.708us	50	50	100.00
V2	trigger_clear_test	aes_clear	4.000s	225.173us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	4.000s	302.143us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	184.708us	50	50	100.00
V2	stress	aes_stress	4.000s	119.857us	50	50	100.00
V2	sideload	aes_stress	4.000s	119.857us	50	50	100.00
		aes_sideload	3.000s	62.203us	50	50	100.00
V2	deinitialization	aes_deinit	4.000s	124.095us	50	50	100.00
V2	stress_all	aes_stress_all	47.000s	3.633ms	10	10	100.00
V2	alert_test	aes_alert_test	2.000s	52.254us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	88.521us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	88.521us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	62.803us	5	5	100.00
		aes_csr_rw	3.000s	140.115us	20	20	100.00
		aes_csr_aliasing	3.000s	94.343us	5	5	100.00
		aes_same_csr_outstanding	3.000s	261.031us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	62.803us	5	5	100.00
		aes_csr_rw	3.000s	140.115us	20	20	100.00
		aes_csr_aliasing	3.000s	94.343us	5	5	100.00
		aes_same_csr_outstanding	3.000s	261.031us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	7.000s	952.577us	50	50	100.00
V2S	fault_inject	aes_fi	4.000s	266.251us	50	50	100.00
		aes_control_fi	33.000s	10.006ms	273	300	91.00
		aes_cipher_fi	30.000s	10.003ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	91.358us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	91.358us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	91.358us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	91.358us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	419.877us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.054ms	5	5	100.00
		aes_tl_intg_err	3.000s	180.297us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	180.297us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	184.708us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	91.358us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	197.434us	50	50	100.00
		aes_stress	4.000s	119.857us	50	50	100.00
		aes_alert_reset	4.000s	184.708us	50	50	100.00
		aes_core_fi	3.900m	10.011ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	91.358us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	101.362us	50	50	100.00
		aes_stress	4.000s	119.857us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	119.857us	50	50	100.00
		aes_sideload	3.000s	62.203us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	101.362us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	101.362us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	101.362us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	101.362us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	101.362us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	119.857us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	119.857us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	266.251us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	266.251us	50	50	100.00
		aes_control_fi	33.000s	10.006ms	273	300	91.00
		aes_cipher_fi	30.000s	10.003ms	329	350	94.00
		aes_ctr_fi	3.000s	166.895us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	266.251us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	266.251us	50	50	100.00
		aes_control_fi	33.000s	10.006ms	273	300	91.00
		aes_cipher_fi	30.000s	10.003ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	30.000s	10.003ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	266.251us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	266.251us	50	50	100.00
		aes_control_fi	33.000s	10.006ms	273	300	91.00
		aes_ctr_fi	3.000s	166.895us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	266.251us	50	50	100.00
		aes_control_fi	33.000s	10.006ms	273	300	91.00
		aes_cipher_fi	30.000s	10.003ms	329	350	94.00
		aes_ctr_fi	3.000s	166.895us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	184.708us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	266.251us	50	50	100.00
		aes_control_fi	33.000s	10.006ms	273	300	91.00
		aes_cipher_fi	30.000s	10.003ms	329	350	94.00
		aes_ctr_fi	3.000s	166.895us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	266.251us	50	50	100.00
		aes_control_fi	33.000s	10.006ms	273	300	91.00
		aes_cipher_fi	30.000s	10.003ms	329	350	94.00
		aes_ctr_fi	3.000s	166.895us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	266.251us	50	50	100.00
		aes_control_fi	33.000s	10.006ms	273	300	91.00
		aes_ctr_fi	3.000s	166.895us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	266.251us	50	50	100.00
		aes_control_fi	33.000s	10.006ms	273	300	91.00
		aes_cipher_fi	30.000s	10.003ms	329	350	94.00
V2S		TOTAL			931	985	94.52
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	15.000s	3.846ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1538	1602	96.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.20	97.64	94.67	98.74	93.20	98.07	91.11	98.08	98.19

Failure Buckets

Job timed out after * minutes has 28 failures:
- Test aes_cipher_fi has 12 failures.
  - 14.aes_cipher_fi.61005372073186418747365705388016305235158096411688648076485843072594316655453
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 51.aes_cipher_fi.34905570438922860747745576219663704216789741287124421289022424657954919338693
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/51.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
- Test aes_control_fi has 16 failures.
  - 25.aes_control_fi.97571314036826324748423816992055688341932798531287997305320134055037766635912
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 27.aes_control_fi.79356237353755735188569799626082103228523851869462210861407817992023882282194
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 14 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 4.aes_control_fi.73187853201782293019252746674936162152673624696230415346382367774083997519387
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10047182479 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10047182479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 93.aes_control_fi.109838134469406089023306967603349022143087053796480938945677060012878780223408
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/93.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010294241 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010294241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 29.aes_cipher_fi.22019647735221221402535433269928201559432427305911028043115418248170931200879
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10017706990 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017706990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 31.aes_cipher_fi.92249956930834557457693199218763621775478782569447528076113703403922636015688
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012867000 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012867000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.33565680836611492954506859611068984059997822149034582226857168094088662213484
Line 418, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  95372162 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  95372162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.66325372675967153991094973276797032089247219801422438633372216623625875687616
Line 598, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 307006836 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 307006836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 27.aes_core_fi.68034169878101793747632490644576562509743305270438597474476535524582978061647
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019942122 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019942122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 41.aes_core_fi.6169538901139001511141570062889223484588196560664880672722406875872567491864
    Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009396902 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009396902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.10304360342029775975570891471342709739399210947412035115058816999272162283424
    Line 701, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 635214432 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 635214432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.54858698054184761190204227582044054564065934674655215518963248578122486644636
    Line 150, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  36072326 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  36072326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 2 failures:

Test aes_core_fi has 2 failures.

34.aes_core_fi.71737249518920664406730834571406396460719185844300675711018344199093767373833
Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/34.aes_core_fi/latest/run.log

  UVM_FATAL @ 10043504622 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x95988b84, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10043504622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.aes_core_fi.64856043542480832140469590207884598760247827990103376954310467582499192881499
Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/47.aes_core_fi/latest/run.log

  UVM_FATAL @ 10011058705 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x90d79384, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10011058705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 53.aes_core_fi.3702928400685090518292627530141259874833432921565230154827406511114798217666
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019556110 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019556110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```