CSRNG Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	241.390us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	46.789us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	104.231us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	47.000s	4.972ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	157.473us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	155.343us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	104.231us	20	20	100.00
		csrng_csr_aliasing	5.000s	157.473us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	32.000s	1.909ms	198	200	99.00
V2	alerts	csrng_alert	55.000s	5.061ms	500	500	100.00
V2	err	csrng_err	4.000s	91.196us	493	500	98.60
V2	cmds	csrng_cmds	8.100m	41.833ms	50	50	100.00
V2	life cycle	csrng_cmds	8.100m	41.833ms	50	50	100.00
V2	stress_all	csrng_stress_all	30.283m	109.824ms	43	50	86.00
V2	intr_test	csrng_intr_test	4.000s	101.687us	50	50	100.00
V2	alert_test	csrng_alert_test	11.000s	206.696us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.000s	361.736us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.000s	361.736us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	46.789us	5	5	100.00
		csrng_csr_rw	4.000s	104.231us	20	20	100.00
		csrng_csr_aliasing	5.000s	157.473us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	740.851us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	46.789us	5	5	100.00
		csrng_csr_rw	4.000s	104.231us	20	20	100.00
		csrng_csr_aliasing	5.000s	157.473us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	740.851us	20	20	100.00
V2		TOTAL			1424	1440	98.89
V2S	tl_intg_err	csrng_sec_cm	4.000s	96.342us	5	5	100.00
		csrng_tl_intg_err	16.000s	2.031ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	3.000s	40.127us	50	50	100.00
		csrng_csr_rw	4.000s	104.231us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	55.000s	5.061ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	30.283m	109.824ms	43	50	86.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
		csrng_sec_cm	4.000s	96.342us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
		csrng_sec_cm	4.000s	96.342us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
		csrng_sec_cm	4.000s	96.342us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
		csrng_sec_cm	4.000s	96.342us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
		csrng_sec_cm	4.000s	96.342us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
		csrng_sec_cm	4.000s	96.342us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
		csrng_sec_cm	4.000s	96.342us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	55.000s	5.061ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	30.283m	109.824ms	43	50	86.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	55.000s	5.061ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	2.031ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
		csrng_sec_cm	4.000s	96.342us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
		csrng_sec_cm	4.000s	96.342us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	32.000s	1.909ms	198	200	99.00
		csrng_err	4.000s	91.196us	493	500	98.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	12.367m	60.875ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1614	1630	99.02

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.63	98.53	96.37	99.94	97.08	92.08	100.00	95.61	90.67

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed has 9 failures:

  • Test csrng_intr has 2 failures.

    • 27.csrng_intr.23967850776457456256260519673231406424684075952703439051565889170315725604417
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/27.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 392396318 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @ 392396318 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @ 392396318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 57.csrng_intr.4231481752084376383415265694396027441682603396958837698867967238877218251122
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/57.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 54167671 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  54167671 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  54167671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test csrng_err has 7 failures.

    • 124.csrng_err.15879014253721493066378665128001730406965716834821554637718629970761123756400
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/124.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 7850630 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @   7850630 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   7850630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 126.csrng_err.29507981490994662460313719223348399002126410777438606632326151529047730319502
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/126.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 10542072 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  10542072 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  10542072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 7 failures:
  • Test csrng_stress_all has 7 failures.

    • 15.csrng_stress_all.106810811357891345257022001261924970646592172887008751916375094851799501358208
      Line 158, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log

        UVM_ERROR @ 1566367729 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 1566367729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 18.csrng_stress_all.28830088271201011652336972370744277973577736860108869545084119839698715252741
      Line 155, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/18.csrng_stress_all/latest/run.log

        UVM_ERROR @ 15648379125 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 15648379125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.