DMA Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	1.996ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	5.740ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	1.745ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	70.713us	5	5	100.00
V1	csr_rw	dma_csr_rw	2.000s	145.245us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	10.000s	306.711us	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	155.596us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	104.960us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	145.245us	20	20	100.00
		dma_csr_aliasing	6.000s	155.596us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	2.317m	6.715ms	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	13.200m	947.666ms	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	20.050m	94.838ms	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	20.050m	94.838ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	13.200m	947.666ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	16.367m	84.053ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	20.050m	94.838ms	3	3	100.00
V2	dma_abort	dma_abort	16.000s	4.070ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	4.367m	17.273ms	3	3	100.00
V2	alert_test	dma_alert_test	2.000s	47.436us	50	50	100.00
V2	intr_test	dma_intr_test	2.000s	43.957us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	432.227us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	432.227us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	70.713us	5	5	100.00
		dma_csr_rw	2.000s	145.245us	20	20	100.00
		dma_csr_aliasing	6.000s	155.596us	5	5	100.00
		dma_same_csr_outstanding	3.000s	176.520us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	70.713us	5	5	100.00
		dma_csr_rw	2.000s	145.245us	20	20	100.00
		dma_csr_aliasing	6.000s	155.596us	5	5	100.00
		dma_same_csr_outstanding	3.000s	176.520us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	27.000s	1.010ms	5	5	100.00
		dma_generic_stress	16.367m	84.053ms	5	5	100.00
		dma_handshake_stress	20.050m	94.838ms	3	3	100.00
V2S	dma_config_lock	dma_config_lock	9.000s	649.526us	15	15	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	1.204ms	20	20	100.00
		dma_sec_cm	2.000s	10.891us	5	5	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	2.850m	33.845ms	25	25	100.00
		dma_longer_transfer	13.000s	941.715us	5	5	100.00
		dma_stress_all_with_rand_reset	5.000s	2.572ms	0	1	0.00
		TOTAL			394	395	99.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.29	97.38	95.83	96.89	96.04	77.37	92.96	95.97	77.31

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.30126969257424180382113056646212371137424537299779142081128627406300001130191
      Line 99, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2571546719ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2571546719ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---