EDN Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.220s 20.455us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.840s 231.132us 5 5 100.00
V1 csr_rw edn_csr_rw 1.080s 16.023us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.590s 140.613us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.390s 69.303us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.550s 44.653us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.080s 16.023us 20 20 100.00
edn_csr_aliasing 1.390s 69.303us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 3.090s 302.736us 300 300 100.00
V2 csrng_commands edn_genbits 3.090s 302.736us 300 300 100.00
V2 genbits edn_genbits 3.090s 302.736us 300 300 100.00
V2 interrupts edn_intr 1.190s 35.000us 50 50 100.00
V2 alerts edn_alert 1.330s 35.244us 200 200 100.00
V2 errs edn_err 1.480s 30.842us 100 100 100.00
V2 disable edn_disable 1.100s 14.223us 50 50 100.00
edn_disable_auto_req_mode 1.430s 36.028us 50 50 100.00
V2 stress_all edn_stress_all 5.170s 588.067us 50 50 100.00
V2 intr_test edn_intr_test 1.020s 12.946us 50 50 100.00
V2 alert_test edn_alert_test 1.830s 106.493us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.020s 526.774us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.020s 526.774us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.840s 231.132us 5 5 100.00
edn_csr_rw 1.080s 16.023us 20 20 100.00
edn_csr_aliasing 1.390s 69.303us 5 5 100.00
edn_same_csr_outstanding 1.180s 68.189us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.840s 231.132us 5 5 100.00
edn_csr_rw 1.080s 16.023us 20 20 100.00
edn_csr_aliasing 1.390s 69.303us 5 5 100.00
edn_same_csr_outstanding 1.180s 68.189us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.080s 1.158ms 5 5 100.00
edn_tl_intg_err 2.390s 286.820us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.410s 21.265us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.330s 35.244us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.080s 1.158ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.080s 1.158ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.080s 1.158ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.080s 1.158ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.330s 35.244us 200 200 100.00
edn_sec_cm 7.080s 1.158ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.330s 35.244us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.390s 286.820us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.353m 5.521ms 28 50 56.00
V3 TOTAL 28 50 56.00
TOTAL 1108 1130 98.05

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.31 98.87 94.29 97.07 90.12 96.33 97.56 92.94

Failure Buckets