HMAC Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	11.710s	1.256ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.240s	210.129us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.280s	57.437us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.110s	3.948ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.350s	312.559us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.343m	102.182ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.280s	57.437us	20	20	100.00
		hmac_csr_aliasing	6.350s	312.559us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.000m	11.716ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.430m	1.437ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.235m	6.806ms	30	30	100.00
		hmac_test_sha384_vectors	8.942m	14.830ms	75	75	100.00
		hmac_test_sha512_vectors	8.333m	13.599ms	75	75	100.00
		hmac_test_hmac256_vectors	15.110s	951.074us	50	50	100.00
		hmac_test_hmac384_vectors	17.900s	1.754ms	60	60	100.00
		hmac_test_hmac512_vectors	17.690s	353.570us	75	75	100.00
V2	burst_wr	hmac_burst_wr	44.070s	7.691ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	15.383m	17.964ms	10	10	100.00
V2	error	hmac_error	1.558m	10.137ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.497m	1.830ms	10	10	100.00
V2	save_and_restore	hmac_smoke	11.710s	1.256ms	10	10	100.00
		hmac_long_msg	1.000m	11.716ms	10	10	100.00
		hmac_back_pressure	1.430m	1.437ms	25	25	100.00
		hmac_datapath_stress	15.383m	17.964ms	10	10	100.00
		hmac_burst_wr	44.070s	7.691ms	50	50	100.00
		hmac_stress_all	1.079h	86.416ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	11.710s	1.256ms	10	10	100.00
		hmac_long_msg	1.000m	11.716ms	10	10	100.00
		hmac_back_pressure	1.430m	1.437ms	25	25	100.00
		hmac_datapath_stress	15.383m	17.964ms	10	10	100.00
		hmac_wipe_secret	1.497m	1.830ms	10	10	100.00
		hmac_test_sha256_vectors	4.235m	6.806ms	30	30	100.00
		hmac_test_sha384_vectors	8.942m	14.830ms	75	75	100.00
		hmac_test_sha512_vectors	8.333m	13.599ms	75	75	100.00
		hmac_test_hmac256_vectors	15.110s	951.074us	50	50	100.00
		hmac_test_hmac384_vectors	17.900s	1.754ms	60	60	100.00
		hmac_test_hmac512_vectors	17.690s	353.570us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	11.710s	1.256ms	10	10	100.00
		hmac_long_msg	1.000m	11.716ms	10	10	100.00
		hmac_back_pressure	1.430m	1.437ms	25	25	100.00
		hmac_datapath_stress	15.383m	17.964ms	10	10	100.00
		hmac_burst_wr	44.070s	7.691ms	50	50	100.00
		hmac_error	1.558m	10.137ms	10	10	100.00
		hmac_wipe_secret	1.497m	1.830ms	10	10	100.00
		hmac_test_sha256_vectors	4.235m	6.806ms	30	30	100.00
		hmac_test_sha384_vectors	8.942m	14.830ms	75	75	100.00
		hmac_test_sha512_vectors	8.333m	13.599ms	75	75	100.00
		hmac_test_hmac256_vectors	15.110s	951.074us	50	50	100.00
		hmac_test_hmac384_vectors	17.900s	1.754ms	60	60	100.00
		hmac_test_hmac512_vectors	17.690s	353.570us	75	75	100.00
		hmac_stress_all	1.079h	86.416ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.079h	86.416ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.950s	31.103us	50	50	100.00
V2	intr_test	hmac_intr_test	0.980s	18.467us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.030s	169.263us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.030s	169.263us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.240s	210.129us	5	5	100.00
		hmac_csr_rw	1.280s	57.437us	20	20	100.00
		hmac_csr_aliasing	6.350s	312.559us	5	5	100.00
		hmac_same_csr_outstanding	2.850s	144.040us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.240s	210.129us	5	5	100.00
		hmac_csr_rw	1.280s	57.437us	20	20	100.00
		hmac_csr_aliasing	6.350s	312.559us	5	5	100.00
		hmac_same_csr_outstanding	2.850s	144.040us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.470s	100.160us	5	5	100.00
		hmac_tl_intg_err	4.960s	1.307ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.960s	1.307ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	11.710s	1.256ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.320s	648.280us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.933m	4.515ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	3.410s	105.466us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.19	99.95	96.96	100.00	100.00	99.83	97.61	100.00