I2C Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: `2bd4e85`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.260m	8.113ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	36.840s	1.687ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.130s	36.166us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.110s	41.823us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.690s	1.387ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.000s	222.903us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.620s	33.657us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.110s	41.823us	20	20	100.00
		i2c_csr_aliasing	2.000s	222.903us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	6.930s	142.620us	4	50	8.00
V2	host_stress_all	i2c_host_stress_all	44.061m	98.166ms	14	50	28.00
V2	host_maxperf	i2c_host_perf	31.473m	73.378ms	48	50	96.00
V2	host_override	i2c_host_override	1.050s	19.503us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.484m	19.406ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.474m	8.693ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.730s	705.011us	50	50	100.00
		i2c_host_fifo_fmt_empty	24.340s	3.560ms	50	50	100.00
		i2c_host_fifo_reset_rx	11.580s	209.412us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.920m	3.890ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	39.100s	972.322us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.060s	142.225us	18	50	36.00
V2	target_glitch	i2c_target_glitch	3.700s	2.015ms	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	12.441m	52.904ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	7.990s	903.668us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.145m	3.352ms	50	50	100.00
		i2c_target_intr_smoke	9.570s	9.543ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.490s	320.073us	50	50	100.00
		i2c_target_fifo_reset_tx	2.640s	849.092us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	23.500m	67.700ms	50	50	100.00
		i2c_target_stress_rd	1.145m	3.352ms	50	50	100.00
		i2c_target_intr_stress_wr	5.824m	23.265ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	10.140s	6.810ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.830m	3.912ms	42	50	84.00
V2	bad_address	i2c_target_bad_addr	9.460s	2.537ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	43.790s	10.011ms	22	50	44.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.070s	4.868ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.150s	450.006us	48	50	96.00
V2	host_mode_config_perf	i2c_host_perf	31.473m	73.378ms	48	50	96.00
		i2c_host_perf_precise	7.418m	24.449ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	39.100s	972.322us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	27.810s	1.775ms	47	50	94.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.290s	2.518ms	50	50	100.00
		i2c_target_nack_acqfull_addr	4.060s	565.728us	50	50	100.00
		i2c_target_nack_txstretch	2.460s	763.903us	29	50	58.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	29.550s	836.138us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.630s	577.682us	50	50	100.00
V2	alert_test	i2c_alert_test	0.990s	17.443us	50	50	100.00
V2	intr_test	i2c_intr_test	1.120s	24.605us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.720s	135.988us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.720s	135.988us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.130s	36.166us	5	5	100.00
		i2c_csr_rw	1.110s	41.823us	20	20	100.00
		i2c_csr_aliasing	2.000s	222.903us	5	5	100.00
		i2c_same_csr_outstanding	1.590s	64.508us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.130s	36.166us	5	5	100.00
		i2c_csr_rw	1.110s	41.823us	20	20	100.00
		i2c_csr_aliasing	2.000s	222.903us	5	5	100.00
		i2c_same_csr_outstanding	1.590s	64.508us	20	20	100.00
V2		TOTAL			1612	1792	89.96
V2S	tl_intg_err	i2c_tl_intg_err	2.350s	173.658us	20	20	100.00
		i2c_sec_cm	1.290s	55.249us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.350s	173.658us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	1.113m	1.067ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.320s	1.303ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	19.190s	2.027ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1792	2042	87.76

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.16	97.31	89.33	74.17	48.21	93.97	96.41	89.75

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 82 failures:

Test i2c_host_error_intr has 46 failures.

0.i2c_host_error_intr.2327428457359527285104818634500193861622217833199794839575375197593413446470
Line 107, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 304891569 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 304891569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.91787073443383492217164082233813609192628336171804143274904896223149882439620
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  57768274 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  57768274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 44 more failures.

Test i2c_host_mode_toggle has 9 failures.

0.i2c_host_mode_toggle.22982839976080210685069095371545809015933047740210665066144206991743459063515
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  33873543 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  33873543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_mode_toggle.37010328466717176555754960859151112993093079206783332362405281256980775355822
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  25036267 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  25036267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_host_stress_all has 23 failures.

1.i2c_host_stress_all.45461145652864402428917826213582826627315897379776506385486029864923985609181
Line 111, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 1490430072 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 1490430072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stress_all.104198203755970118699238150573240415582894552385809087551673756777846616522011
Line 144, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 15301168008 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 15301168008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 21 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

1.i2c_target_stress_all_with_rand_reset.91076002353030447831773406527199638540647313156314014121817938850363973870060
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   8571243 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @   8571243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all_with_rand_reset.103785467321579614832237690779620155716301990334865768789291905176730558087802
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 486192427 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 486192427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 30 failures:
- Test i2c_target_unexp_stop has 30 failures.
  - 1.i2c_target_unexp_stop.77489456880310182585591514529705466001292431085510564669796020866117707474917
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1302819421 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 249 [0xf9])
  UVM_INFO @ 1302819421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.1992501737715341394456416481717114836661367457231519184591264034688043679112
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  60781605 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 33 [0x21])
  UVM_INFO @  60781605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 28 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 28 failures:
- Test i2c_target_hrst has 28 failures.
  - 0.i2c_target_hrst.70620710276808696898540210484692130799488601779676214823131602409539068819315
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10011348543 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10011348543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_hrst.41065940037583153141249782011698566955022073613856544550880220766415060439525
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10004172940 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10004172940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 26 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 21 failures:
- Test i2c_target_nack_txstretch has 21 failures.
  - 0.i2c_target_nack_txstretch.31072478648930891049131016147162527522563137637869493015468603607603939672028
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 669751460 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 669751460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_nack_txstretch.9788512147876164776786574019019406977833900162521594630661338003158099603915
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 335960439 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 335960439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.62435724517972788698166674893890348692717478212761769298040632258922343411891
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 801161045 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 801161045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.109089775826046303518100679079696628553388223231295894055139831509421271806430
Line 141, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 932780119 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 932780119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 5 failures.

2.i2c_target_stress_all_with_rand_reset.62871749144380031135651517560324322887785613116711515419906191779013743936384
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2026637081 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2026637081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.46419265226162909622867349918289211196230569172429858475596040207079190506596
Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1043918473 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1043918473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 14 failures:
- Test i2c_target_unexp_stop has 14 failures.
  - 0.i2c_target_unexp_stop.71198785042470332536128192107239029031585593471809762116233630245115084107702
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 163204755 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 163204755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.83586120279866094655826327618283149725232328674581829327148109489512997700103
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 102396681 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 102396681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 14 failures:

Test i2c_host_mode_toggle has 4 failures.

1.i2c_host_mode_toggle.18100658966895038847041990640552623422258348329796754038544812974204476914195
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 254570901 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @92892

18.i2c_host_mode_toggle.63631517133532906321826480822602908288286444667006171492474273352599807730226
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/18.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 607789471 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @43100

... and 2 more failures.

Test i2c_host_stress_all has 10 failures.

6.i2c_host_stress_all.95328087081772222136556808099419807629376783753142165990919226888339984318119
Line 148, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 53756867100 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3713913

11.i2c_host_stress_all.74204738984545120787614651913392571039595327610005921049538313778164788875808
Line 162, in log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 218616766660 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5145701

... and 8 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 12 failures:

Test i2c_host_mode_toggle has 12 failures.

5.i2c_host_mode_toggle.14631606430447983424070416943398960625095501077959979839020435972426500245674
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  67483272 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

7.i2c_host_mode_toggle.26929596506753504901300503142637348201680576600487615195525818567000383701455
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  50946858 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 10 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 8 failures:
- Test i2c_target_stretch has 8 failures.
  - 2.i2c_target_stretch.108241711345790683603629488690898872036673887986693880943326129800503535931127
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011305016 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011305016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_stretch.86466140421689160559098051586923843621696496765430475080177953267064747505117
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10002383720 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10002383720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:

Test i2c_target_unexp_stop has 6 failures.

16.i2c_target_unexp_stop.33712491647517400159273103606541966432195493753216755753551859775845630943467
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 287972214 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 287972214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.i2c_target_unexp_stop.63335748249616582871929158724404559256881662471541322339127125020863697076462
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/38.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 188681340 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 188681340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 6 failures:
- Test i2c_host_mode_toggle has 6 failures.
  - 17.i2c_host_mode_toggle.2031366506978769810743843251893530374697277488453812221031056825719169489017
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/17.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  54708613 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x19ef5d14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  54708613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 25.i2c_host_mode_toggle.61276193078908818645030642699248402757197540486074238684347168205479225688967
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/25.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  32385116 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x277ec114, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  32385116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
- Test i2c_target_fifo_watermarks_tx has 2 failures.
  - 2.i2c_target_fifo_watermarks_tx.61959289061704012923296406689488266539700117937450633295471158732356887978630
    Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 17.i2c_target_fifo_watermarks_tx.5502319536605782448496588145810512369250384211134049229954615730738808561303
    Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
- Test i2c_target_tx_stretch_ctrl has 3 failures.
  - 10.i2c_target_tx_stretch_ctrl.62818104063784410823599939434259320845979805545831954035601188845770517835288
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 12.i2c_target_tx_stretch_ctrl.85295630217311283600849511141244709616804241297119543483439232581269131764770
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
Job timed out after * minutes has 3 failures:
- Test i2c_host_perf has 1 failures.
  - 15.i2c_host_perf.11248748046133520637718217993141771305439754653839232408476016189862188435204
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/15.i2c_host_perf/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_stress_all has 2 failures.
  - 24.i2c_host_stress_all.49947511704377332244369854396446547643688131019245086049002853384362573923885
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 27.i2c_host_stress_all.42265187061337411507852301521270512737856277997021062172138561273455025349871
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.29607836758162515676794603950673723878334240807909270594508030805680910239975
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 530364931 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 530364931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.92545242652272820414641366063929917802212061864260945039119962969020694949020
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 2014641381 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 2014641381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.107108131121093335019308921907070048378795222866706707554010845702565905865886
    Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 915502881 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 915502881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 20.i2c_host_stress_all.5148972029584371692607446075074489187162199025915226563931378402747787801577
    Line 88, in log /nightly/current_run/scratch/master/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 46.i2c_host_mode_toggle.24001253490493973908091504874933972273681044615837950815299664005023876975929
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/46.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=68) has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 49.i2c_host_perf.107024364670524298785363931414824760539833094622598079978977513324147475976468
    Line 77, in log /nightly/current_run/scratch/master/i2c-sim-vcs/49.i2c_host_perf/latest/run.log
```
  UVM_FATAL @ 10282268046 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.fmtfull (addr=0xe3a95314, Comparison=CompareOpEq, exp_data=0x0, call_count=68)
  UVM_INFO @ 10282268046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```