KEYMGR Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	20.330s	2.567ms	50	50	100.00
V1	random	keymgr_random	1.150m	14.228ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.810s	54.594us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.560s	21.264us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	21.160s	2.457ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.350s	1.957ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.470s	108.973us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.560s	21.264us	20	20	100.00
		keymgr_csr_aliasing	9.350s	1.957ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.583m	5.378ms	49	50	98.00
V2	sideload	keymgr_sideload	47.150s	28.327ms	50	50	100.00
		keymgr_sideload_kmac	47.270s	3.372ms	50	50	100.00
		keymgr_sideload_aes	37.890s	3.116ms	50	50	100.00
		keymgr_sideload_otbn	30.170s	2.372ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	19.550s	1.094ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	20.220s	4.519ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	9.340s	648.679us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	51.730s	18.741ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	58.880s	4.713ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	18.250s	2.194ms	50	50	100.00
V2	stress_all	keymgr_stress_all	1.748m	8.093ms	49	50	98.00
V2	intr_test	keymgr_intr_test	1.200s	17.553us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.230s	44.481us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.540s	425.882us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.540s	425.882us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.810s	54.594us	5	5	100.00
		keymgr_csr_rw	1.560s	21.264us	20	20	100.00
		keymgr_csr_aliasing	9.350s	1.957ms	5	5	100.00
		keymgr_same_csr_outstanding	3.640s	1.859ms	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.810s	54.594us	5	5	100.00
		keymgr_csr_rw	1.560s	21.264us	20	20	100.00
		keymgr_csr_aliasing	9.350s	1.957ms	5	5	100.00
		keymgr_same_csr_outstanding	3.640s	1.859ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
		keymgr_tl_intg_err	7.150s	1.062ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.410s	299.424us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.410s	299.424us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.410s	299.424us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.410s	299.424us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.780s	662.582us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.150s	1.062ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.410s	299.424us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.583m	5.378ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.150m	14.228ms	50	50	100.00
		keymgr_csr_rw	1.560s	21.264us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.150m	14.228ms	50	50	100.00
		keymgr_csr_rw	1.560s	21.264us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.150m	14.228ms	50	50	100.00
		keymgr_csr_rw	1.560s	21.264us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	20.220s	4.519ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	58.880s	4.713ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	58.880s	4.713ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.150m	14.228ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	28.390s	8.749ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	38.090s	3.427ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	20.220s	4.519ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	38.090s	3.427ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	38.090s	3.427ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	38.090s	3.427ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.830s	2.269ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	38.090s	3.427ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	19.560s	7.126ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1089	1110	98.11

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.66	99.13	98.15	98.51	100.00	99.01	97.71	91.13

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
  • Test keymgr_stress_all_with_rand_reset has 19 failures.

    • 0.keymgr_stress_all_with_rand_reset.74885892072574161757985874737616358731515477718441074913164702838795746689929
      Line 789, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1141425327 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1141425327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.keymgr_stress_all_with_rand_reset.6996303672503175256289529854850439119367888893175742572101886944979439054659
      Line 399, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 409076410 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 409076410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_stress_all has 1 failures.

    • 36.keymgr_stress_all.59320082605750613007011563378179215615613961120251158483085877157219718994699
      Line 1398, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/36.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 2477915447 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 2477915447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_cfg_regwen has 1 failures.

    • 43.keymgr_cfg_regwen.89813003075235593344220408741971677403331602561839610672991019721260733314921
      Line 138, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @   6394969 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @   6394969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---