KEYMGR_DPE Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	4.977m	58.204ms	49	50	98.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.470s	97.193us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.350s	25.022us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	12.070s	2.386ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	5.950s	85.997us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.930s	262.399us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.350s	25.022us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.950s	85.997us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	intr_test	keymgr_dpe_intr_test	1.230s	14.815us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.310s	42.210us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.960s	476.329us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.960s	476.329us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.470s	97.193us	5	5	100.00
		keymgr_dpe_csr_rw	1.350s	25.022us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.950s	85.997us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.280s	1.760ms	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.470s	97.193us	5	5	100.00
		keymgr_dpe_csr_rw	1.350s	25.022us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.950s	85.997us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.280s	1.760ms	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	14.030s	877.580us	5	5	100.00
		keymgr_dpe_tl_intg_err	6.830s	1.126ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.840s	432.140us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.840s	432.140us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.840s	432.140us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.840s	432.140us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	5.820s	820.082us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	14.030s	877.580us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	14.030s	877.580us	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			309	310	99.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.59	97.62	90.31	63.04	75.68	94.61	97.62	17.25

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
  • Test keymgr_dpe_smoke has 1 failures.

    • 36.keymgr_dpe_smoke.84361341754059524572064560078288458021238006779494969890679724607529514781108
      Line 4382, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/36.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 2485190234 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 2485190234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---