KMAC/MASKED Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: `2bd4e85`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.986m	14.376ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.500s	55.208us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	23.810us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.340s	1.206ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.640s	749.775us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.280s	814.729us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	23.810us	20	20	100.00
		kmac_csr_aliasing	6.640s	749.775us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.010s	36.413us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	84.492us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.788m	89.914ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.043m	80.343ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.062m	291.987ms	5	5	100.00
		kmac_test_vectors_sha3_256	34.409m	175.242ms	5	5	100.00
		kmac_test_vectors_sha3_384	29.757m	69.848ms	5	5	100.00
		kmac_test_vectors_sha3_512	23.691m	641.026ms	5	5	100.00
		kmac_test_vectors_shake_128	38.983m	71.962ms	5	5	100.00
		kmac_test_vectors_shake_256	35.234m	244.961ms	5	5	100.00
		kmac_test_vectors_kmac	3.300s	233.270us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.270s	144.835us	5	5	100.00
V2	sideload	kmac_sideload	8.428m	22.607ms	50	50	100.00
V2	app	kmac_app	5.680m	27.184ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.963m	10.138ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.100m	166.013ms	50	50	100.00
V2	error	kmac_error	7.838m	59.842ms	50	50	100.00
V2	key_error	kmac_key_error	17.540s	6.840ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.340s	819.832us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.780s	1.243ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	49.320s	8.392ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.084m	7.824ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.470s	755.966us	50	50	100.00
V2	stress_all	kmac_stress_all	37.471m	423.687ms	48	50	96.00
V2	intr_test	kmac_intr_test	1.040s	15.562us	50	50	100.00
V2	alert_test	kmac_alert_test	1.360s	161.993us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.220s	221.780us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.220s	221.780us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.500s	55.208us	5	5	100.00
		kmac_csr_rw	1.180s	23.810us	20	20	100.00
		kmac_csr_aliasing	6.640s	749.775us	5	5	100.00
		kmac_same_csr_outstanding	2.960s	117.330us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.500s	55.208us	5	5	100.00
		kmac_csr_rw	1.180s	23.810us	20	20	100.00
		kmac_csr_aliasing	6.640s	749.775us	5	5	100.00
		kmac_same_csr_outstanding	2.960s	117.330us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.090s	221.805us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.090s	221.805us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.090s	221.805us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.090s	221.805us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.690s	4.373ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.635m	7.577ms	5	5	100.00
		kmac_tl_intg_err	4.080s	2.788ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.080s	2.788ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.470s	755.966us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.986m	14.376ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.428m	22.607ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.090s	221.805us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.635m	7.577ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.635m	7.577ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.635m	7.577ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.986m	14.376ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.470s	755.966us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.635m	7.577ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.852m	32.134ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.986m	14.376ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.213m	10.510ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			935	940	99.47

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.33	99.20	94.45	99.89	80.99	97.08	97.83	97.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 2.kmac_stress_all_with_rand_reset.31599270993418597931628516519210642527985219940328983181242728923819392956324
    Line 329, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18781378002 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 18781378002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.kmac_stress_all_with_rand_reset.14805657030748043027090566611422453703019354658481548598329631390457862696259
    Line 304, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14764279192 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 14764279192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *

has 2 failures:

Test kmac_stress_all has 2 failures.

0.kmac_stress_all.34124519460137911960574923788400900153847837127802721181926181209886345105939
Line 121, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log

  UVM_ERROR @ 5195293462 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 5195293462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_stress_all.54672164268331937954967956564882419188543613704096908158264260749097797308853
Line 117, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_stress_all/latest/run.log

  UVM_ERROR @ 2698686452 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 2698686452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---