MBX Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.333m	5.378ms	2	2	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.000s	21.359us	5	5	100.00
V1	csr_rw	mbx_csr_rw	2.000s	40.660us	20	20	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	7.000s	3.472ms	5	5	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.000s	111.598us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	3.000s	30.051us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	40.660us	20	20	100.00
		mbx_csr_aliasing	2.000s	111.598us	5	5	100.00
V1		TOTAL			57	57	100.00
V2	mbx_stress	mbx_stress	24.000s	1.016ms	2	2	100.00
V2	mbx_max_activity	mbx_stress_zero_delays	1.017m	7.562ms	1	2	50.00
V2	mbx_imbx_oob	mbx_imbx_oob	45.000s	4.290ms	1	2	50.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	24.000s	561.897us	5	5	100.00
V2	alert_test	mbx_alert_test	3.000s	147.027us	50	50	100.00
V2	intr_test	mbx_intr_test	2.000s	76.956us	50	50	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	5.000s	149.257us	20	20	100.00
V2	tl_d_illegal_access	mbx_tl_errors	5.000s	149.257us	20	20	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.000s	21.359us	5	5	100.00
		mbx_csr_rw	2.000s	40.660us	20	20	100.00
		mbx_csr_aliasing	2.000s	111.598us	5	5	100.00
		mbx_same_csr_outstanding	3.000s	168.254us	20	20	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.000s	21.359us	5	5	100.00
		mbx_csr_rw	2.000s	40.660us	20	20	100.00
		mbx_csr_aliasing	2.000s	111.598us	5	5	100.00
		mbx_same_csr_outstanding	3.000s	168.254us	20	20	100.00
V2		TOTAL			149	151	98.68
V2S	tl_intg_err	mbx_tl_intg_err	4.000s	1.147ms	20	20	100.00
		mbx_sec_cm	2.000s	26.420us	5	5	100.00
V2S		TOTAL			25	25	100.00
		TOTAL			231	233	99.14

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.54	96.75	92.07	96.71	91.39	79.74	--	97.01	86.13

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 1 failures:

  • Test mbx_stress_zero_delays has 1 failures.

    • 1.mbx_stress_zero_delays.2926056215090517919914474582240833365677623259839706368977190814266923584087
      Line 548, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @ 719654103 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (1409734955 [0x5406d92b] vs 2687708578 [0xa0332da2]) RDATA read data mismatched
        UVM_INFO @ 719654103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:

  • Test mbx_imbx_oob has 1 failures.

    • 1.mbx_imbx_oob.37824074222455806308119212868599192616182527645686354501463305965802072768271
      Line 94, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_imbx_oob/latest/run.log

        UVM_ERROR @ 528858833 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 528858833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---