OTBN Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 10.000s 136.886us 0 1 0.00
V1 single_binary otbn_single 2.100m 471.320us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 8.000s 46.907us 5 5 100.00
V1 csr_rw otbn_csr_rw 26.000s 14.467us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 11.000s 140.580us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 10.000s 60.297us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 27.000s 70.937us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 26.000s 14.467us 20 20 100.00
otbn_csr_aliasing 10.000s 60.297us 5 5 100.00
V1 mem_walk otbn_mem_walk 55.000s 10.785ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 23.000s 364.870us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 53.000s 208.528us 0 10 0.00
V2 multi_error otbn_multi_err 1.067m 288.410us 0 1 0.00
V2 back_to_back otbn_multi 10.650m 10.844ms 0 10 0.00
V2 stress_all otbn_stress_all 1.617m 939.150us 0 10 0.00
V2 lc_escalation otbn_escalate 25.000s 105.054us 18 60 30.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.000s 16.706us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 23.000s 83.764us 0 10 0.00
V2 alert_test otbn_alert_test 5.000s 22.848us 50 50 100.00
V2 intr_test otbn_intr_test 28.000s 69.306us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 30.000s 102.541us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 30.000s 102.541us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 8.000s 46.907us 5 5 100.00
otbn_csr_rw 26.000s 14.467us 20 20 100.00
otbn_csr_aliasing 10.000s 60.297us 5 5 100.00
otbn_same_csr_outstanding 28.000s 100.588us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 8.000s 46.907us 5 5 100.00
otbn_csr_rw 26.000s 14.467us 20 20 100.00
otbn_csr_aliasing 10.000s 60.297us 5 5 100.00
otbn_same_csr_outstanding 28.000s 100.588us 20 20 100.00
V2 TOTAL 162 246 65.85
V2S mem_integrity otbn_imem_err 11.000s 88.397us 2 10 20.00
otbn_dmem_err 25.000s 92.389us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 14.000s 46.792us 0 5 0.00
otbn_controller_ispr_rdata_err 11.000s 63.151us 0 5 0.00
otbn_mac_bignum_acc_err 17.000s 34.957us 0 5 0.00
otbn_urnd_err 9.000s 54.123us 1 2 50.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 34.576us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 6.000s 16.105us 2 2 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 8.000s 30.890us 10 10 100.00
V2S tl_intg_err otbn_sec_cm 4.183m 2.123ms 1 5 20.00
otbn_tl_intg_err 37.000s 108.471us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 1.350m 469.605us 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S prim_count_check otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_mem_scramble otbn_smoke 10.000s 136.886us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 25.000s 92.389us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 11.000s 88.397us 2 10 20.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 37.000s 108.471us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 25.000s 105.054us 18 60 30.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 11.000s 88.397us 2 10 20.00
otbn_dmem_err 25.000s 92.389us 0 15 0.00
otbn_zero_state_err_urnd 7.000s 16.706us 4 5 80.00
otbn_illegal_mem_acc 8.000s 34.576us 5 5 100.00
otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_scramble_key_sideload otbn_single 2.100m 471.320us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 11.000s 88.397us 2 10 20.00
otbn_dmem_err 25.000s 92.389us 0 15 0.00
otbn_zero_state_err_urnd 7.000s 16.706us 4 5 80.00
otbn_illegal_mem_acc 8.000s 34.576us 5 5 100.00
otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 25.000s 105.054us 18 60 30.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 11.000s 88.397us 2 10 20.00
otbn_dmem_err 25.000s 92.389us 0 15 0.00
otbn_zero_state_err_urnd 7.000s 16.706us 4 5 80.00
otbn_illegal_mem_acc 8.000s 34.576us 5 5 100.00
otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_data_reg_sw_sca otbn_single 2.100m 471.320us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 12.000s 43.236us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 14.000s 55.909us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 2.250m 589.020us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 2.250m 589.020us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 12.000s 63.384us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 18.000s 104.359us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 13.000s 34.079us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 13.000s 34.079us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 9.000s 49.739us 5 7 71.43
V2S sec_cm_data_mem_sec_wipe otbn_single 2.100m 471.320us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 2.100m 471.320us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 2.100m 471.320us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 10.650m 10.844ms 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 2.100m 471.320us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 2.100m 471.320us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 2.900m 723.494us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 2.100m 471.320us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.183m 2.123ms 1 5 20.00
V2S TOTAL 71 163 43.56
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 7.283m 7.246ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 298 585 50.94

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
93.83 97.92 73.12 97.14 78.48 56.44 87.18 80.56 98.29

Failure Buckets