ROM_CTRL/32KB Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: `2bd4e85`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.380s	406.283us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.600s	170.214us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.210s	172.607us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.750s	1.996ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.820s	557.529us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	9.990s	1.027ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.210s	172.607us	20	20	100.00
		rom_ctrl_csr_aliasing	5.820s	557.529us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.800s	170.093us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.860s	550.485us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	4.420s	137.597us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	35.480s	7.931ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.020s	301.129us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	9.450s	535.389us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.480s	684.978us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.480s	684.978us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.600s	170.214us	5	5	100.00
		rom_ctrl_csr_rw	7.210s	172.607us	20	20	100.00
		rom_ctrl_csr_aliasing	5.820s	557.529us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.570s	2.107ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.600s	170.214us	5	5	100.00
		rom_ctrl_csr_rw	7.210s	172.607us	20	20	100.00
		rom_ctrl_csr_aliasing	5.820s	557.529us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.570s	2.107ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.075m	9.760ms	18	20	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	32.570s	6.264ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.424m	3.674ms	2	5	40.00
		rom_ctrl_tl_intg_err	1.358m	334.928us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.424m	3.674ms	2	5	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.424m	3.674ms	2	5	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.075m	9.760ms	18	20	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.075m	9.760ms	18	20	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.075m	9.760ms	18	20	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.075m	9.760ms	18	20	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.075m	9.760ms	18	20	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.424m	3.674ms	2	5	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.424m	3.674ms	2	5	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.380s	406.283us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.380s	406.283us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.380s	406.283us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.358m	334.928us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.075m	9.760ms	18	20	90.00
		rom_ctrl_kmac_err_chk	9.020s	301.129us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.075m	9.760ms	18	20	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.075m	9.760ms	18	20	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.075m	9.760ms	18	20	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	32.570s	6.264ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.424m	3.674ms	2	5	40.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	8.373m	4.797ms	19	20	95.00
V3		TOTAL			19	20	95.00
		TOTAL			260	266	97.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

Test rom_ctrl_sec_cm has 2 failures.

0.rom_ctrl_sec_cm.99685010160437165761147047349065784887779758536677591553810631124955705765139
Line 117, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 31244780ps failed at 31244780ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 31244780ps failed at 31244780ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

1.rom_ctrl_sec_cm.23235639604000059812112327854468057023947202014844076317738614965775625182831
Line 177, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 14150621ps failed at 14150621ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 14150621ps failed at 14150621ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 2 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
  - 4.rom_ctrl_corrupt_sig_fatal_chk.53808512610057340007309867483493121703230290097320934736692820722354702288304
    Line 98, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 4195998590 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 4195998590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.rom_ctrl_corrupt_sig_fatal_chk.95609432362487605467320526526241882326700235105183619073067577229338853064674
    Line 86, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 4056977202 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 4056977202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

4.rom_ctrl_sec_cm.38214536427929467926579422504644903500183258404101739070213793187721579609291
Line 134, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 93063854ps failed at 93063854ps
      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 93063854ps failed at 93063854ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'

UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 6.rom_ctrl_stress_all_with_rand_reset.38206500494960473349475095775649775774248208101060264797038739165359765014495
    Line 96, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 534711725 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 534711725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```