ROM_CTRL/64KB Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	11.810s	386.660us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	13.810s	219.128us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	12.220s	296.761us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.400s	217.104us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.690s	1.075ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.890s	2.673ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	12.220s	296.761us	20	20	100.00
		rom_ctrl_csr_aliasing	10.690s	1.075ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.000s	1.066ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.170s	298.384us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	13.440s	1.109ms	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	52.030s	1.634ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	25.170s	549.358us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	16.640s	1.069ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	16.600s	557.378us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	16.600s	557.378us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	13.810s	219.128us	5	5	100.00
		rom_ctrl_csr_rw	12.220s	296.761us	20	20	100.00
		rom_ctrl_csr_aliasing	10.690s	1.075ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	20.140s	4.147ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	13.810s	219.128us	5	5	100.00
		rom_ctrl_csr_rw	12.220s	296.761us	20	20	100.00
		rom_ctrl_csr_aliasing	10.690s	1.075ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	20.140s	4.147ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.558m	8.402ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.033m	24.833ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	11.952m	1.463ms	0	5	0.00
		rom_ctrl_tl_intg_err	2.456m	353.897us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	11.952m	1.463ms	0	5	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	11.952m	1.463ms	0	5	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.558m	8.402ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.558m	8.402ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.558m	8.402ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.558m	8.402ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.558m	8.402ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	11.952m	1.463ms	0	5	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	11.952m	1.463ms	0	5	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	11.810s	386.660us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	11.810s	386.660us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	11.810s	386.660us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.456m	353.897us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.558m	8.402ms	20	20	100.00
		rom_ctrl_kmac_err_chk	25.170s	549.358us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.558m	8.402ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.558m	8.402ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.558m	8.402ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.033m	24.833ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	11.952m	1.463ms	0	5	0.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.975m	19.267ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.59	95.39	99.59	100.00	99.27	95.49	98.81

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 3 failures:

  • Test rom_ctrl_sec_cm has 3 failures.

    • 1.rom_ctrl_sec_cm.92053712855051502908282719926180744334328659253871286810961773151712674375652
      Line 169, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 25778588ps failed at 25778588ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 29772440ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 29772440ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
      

    • 2.rom_ctrl_sec_cm.81876088539762301006393499279904673959304250489266188280322714781120907074833
      Line 168, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 12020162ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 12020162ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 12020162ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

    • ... and 1 more failures.

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.59981516101838536645425667553239926690816407521872945165758587618726711493338
      Line 120, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 11796707ps failed at 11796707ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 11796707ps failed at 11796707ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 3.rom_ctrl_sec_cm.70407064370311159201175201503753022140739232435297044669094547286016783018873
      Line 558, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 118160451ps failed at 118160451ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 118172216ps failed at 118172216ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'