RV_TIMER Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: `2bd4e85`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.220s	2.299ms	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.780s	15.004us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.830s	14.140us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.350s	285.001us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.910s	30.969us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.450s	46.059us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.830s	14.140us	20	20	100.00
		rv_timer_csr_aliasing	0.910s	30.969us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	11.210s	10.172ms	1	20	5.00
V2	disabled	rv_timer_disabled	3.890s	1.928ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	11.440m	1.316s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	11.440m	1.316s	10	10	100.00
V2	stress	rv_timer_stress_all	7.240s	13.345ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.860s	21.214us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.820s	15.588us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.270s	175.413us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.270s	175.413us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.780s	15.004us	5	5	100.00
		rv_timer_csr_rw	0.830s	14.140us	20	20	100.00
		rv_timer_csr_aliasing	0.910s	30.969us	5	5	100.00
		rv_timer_same_csr_outstanding	1.100s	122.494us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.780s	15.004us	5	5	100.00
		rv_timer_csr_rw	0.830s	14.140us	20	20	100.00
		rv_timer_csr_aliasing	0.910s	30.969us	5	5	100.00
		rv_timer_same_csr_outstanding	1.100s	122.494us	20	20	100.00
V2		TOTAL			191	210	90.95
V2S	tl_intg_err	rv_timer_sec_cm	1.170s	1.040ms	5	5	100.00
		rv_timer_tl_intg_err	1.530s	118.968us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.530s	118.968us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.690s	977.618us	2	10	20.00
V3	max_value	rv_timer_max	0.970s	249.863us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	48.710s	5.187ms	12	20	60.00
V3		TOTAL			14	40	35.00
		TOTAL			305	350	87.14

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.77	100.00	100.00	78.66	--	100.00	96.82	99.12

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 27 failures:
- Test rv_timer_min has 8 failures.
  - 0.rv_timer_min.37316705316496413608762584173875214356630449519904776717608857007178937979340
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @  57228055 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8dc3e704) == 0x1
  UVM_INFO @  57228055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_min.103737167519867870656150498220065034422595698349448316529726015280168633526295
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 218187313 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe9d74704) == 0x1
  UVM_INFO @ 218187313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
- Test rv_timer_random_reset has 19 failures.
  - 0.rv_timer_random_reset.105875160084561866611946089694795983815913131876084383963001267131132403498438
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 10171806413 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x74ef7d04) == 0x1
  UVM_INFO @ 10171806413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.74947753386409019638403779511808949750707626408059918186892080911082338422604
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 372509210 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x31599904) == 0x1
  UVM_INFO @ 372509210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 10 failures:
- Test rv_timer_max has 10 failures.
  - 0.rv_timer_max.44047734757186736523972398736303554890279305881833803213276895743109783833300
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  44162981 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  44162981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.56615859589017049201327834232429890567594358862271876600479519244110710249159
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  45690739 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  45690739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 6 failures:
- Test rv_timer_stress_all_with_rand_reset has 6 failures.
  - 0.rv_timer_stress_all_with_rand_reset.108622313623603564387202929031522623936873880514830074326666196017645030352080
    Line 77, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 298399065 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 298399065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_stress_all_with_rand_reset.58412927233243391082323280544766570559350595004351447439217231343600278057202
    Line 208, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4207765003 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 4207765003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 2 failures:

Test rv_timer_stress_all_with_rand_reset has 2 failures.

14.rv_timer_stress_all_with_rand_reset.81987446719694299434513916185645077713001025790782086884821716246790335029187
Line 158, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/14.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1256207568 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1256207568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.rv_timer_stress_all_with_rand_reset.84186576347487989058060690108272376273059605935252438752161355127498855933996
Line 130, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/17.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11089181000 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 11089181000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---