SPI_DEVICE/1R1W Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: `2bd4e85`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.884m	179.342ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.590s	41.959us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.060s	177.202us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.250s	2.712ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.450s	298.952us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.950s	172.702us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.060s	177.202us	20	20	100.00
		spi_device_csr_aliasing	16.450s	298.952us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	11.120us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.710s	68.788us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	1.200s	35.306us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	1.314us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.940s	4.587us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	5.530s	1.060ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.530s	1.060ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.420s	8.646ms	50	50	100.00
		spi_device_tpm_sts_read	1.490s	403.001us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	38.960s	15.935ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	34.140s	18.259ms	50	50	100.00
		spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	28.900s	33.072ms	50	50	100.00
		spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	28.900s	33.072ms	50	50	100.00
		spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	23.990s	9.078ms	50	50	100.00
		spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	23.990s	9.078ms	50	50	100.00
		spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	23.990s	9.078ms	50	50	100.00
		spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	23.990s	9.078ms	50	50	100.00
		spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	23.990s	9.078ms	50	50	100.00
		spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	25.280s	23.157ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.473m	51.734ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.473m	51.734ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.473m	51.734ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.239m	7.296ms	49	50	98.00
		spi_device_read_buffer_direct	15.910s	4.608ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.473m	51.734ms	50	50	100.00
		spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.643m	131.330ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	36.640s	19.553ms	49	50	98.00
V2	write_enable_disable	spi_device_cfg_cmd	36.640s	19.553ms	49	50	98.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.884m	179.342ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.080m	270.986ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.913m	113.271ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.150s	12.775us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.160s	16.397us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.140s	521.566us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.140s	521.566us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.590s	41.959us	5	5	100.00
		spi_device_csr_rw	3.060s	177.202us	20	20	100.00
		spi_device_csr_aliasing	16.450s	298.952us	5	5	100.00
		spi_device_same_csr_outstanding	4.630s	548.001us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.590s	41.959us	5	5	100.00
		spi_device_csr_rw	3.060s	177.202us	20	20	100.00
		spi_device_csr_aliasing	16.450s	298.952us	5	5	100.00
		spi_device_same_csr_outstanding	4.630s	548.001us	20	20	100.00
V2		TOTAL			938	961	97.61
V2S	tl_intg_err	spi_device_sec_cm	1.520s	98.485us	5	5	100.00
		spi_device_tl_intg_err	18.880s	2.400ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.880s	2.400ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.092m	55.409ms	49	50	98.00
		TOTAL			1126	1151	97.83

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.61	99.11	96.56	71.19	89.36	98.40	94.43	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.34523695976442587522120504934648803354095994481442266699703430618817426874170
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1279930 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[34])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1279930 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1279930 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[930])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.88020957335382031553595993440756239251182424318219127909752170203506131327453
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3210569 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[30])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3210569 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3210569 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[926])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.48320888798281975737652591807741223495874551772917410622229010428408402757953
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   2057499 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x62d1ba [11000101101000110111010] vs 0x0 [0])
  UVM_ERROR @   2092499 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe6a2b4 [111001101010001010110100] vs 0x0 [0])
  UVM_ERROR @   2159499 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7d17b4 [11111010001011110110100] vs 0x0 [0])
  UVM_ERROR @   2234499 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfb8443 [111110111000010001000011] vs 0x0 [0])
  UVM_ERROR @   2260499 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6a5e7c [11010100101111001111100] vs 0x0 [0])

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 3.spi_device_flash_mode_ignore_cmds.40574007732130700062594452752312053290495264293524407532082154490191578543316
    Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (spi_device_scoreboard.sv:2815) [scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 5.spi_device_flash_mode.18032592197857189274183451401211618970734668525195855358856538449871242871699
    Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 5905262944 ps: (spi_device_scoreboard.sv:2815) [uvm_test_top.env.scoreboard] Check failed |(intr_trigger_pending & interrupt_mask) == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5905262944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

29.spi_device_flash_and_tpm.32309983707884222504142597303760717018723704698339486266171863548519582407364
Line 109, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 14024132458 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (10726400 [0xa3ac00] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xa3ac00 != exp 0x0
  UVM_INFO @ 16375893482 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 6/7
  UVM_INFO @ 16482079770 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/14
  UVM_INFO @ 16935266174 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 7/14
  UVM_INFO @ 17803555914 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/14

UVM_ERROR (spi_device_scoreboard.sv:2247) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

48.spi_device_cfg_cmd.68825206300129239943214998905737606912534446431413912427774657701342017815163
Line 82, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 776417407 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8665aa) != exp '{'{other_status:'h278f2, wel:'h1, busy:'h0}, '{other_status:'h373542, wel:'h1, busy:'h0}, '{other_status:'h21996a, wel:'h0, busy:'h0}, '{other_status:'h373542, wel:'h0, busy:'h0}, '{other_status:'h21996a, wel:'h0, busy:'h0}}
  UVM_INFO @ 776625747 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 9, test op = 0xb7
  UVM_ERROR @ 776792419 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8665aa) != exp '{'{other_status:'h278f2, wel:'h1, busy:'h0}, '{other_status:'h373542, wel:'h1, busy:'h0}, '{other_status:'h21996a, wel:'h0, busy:'h0}, '{other_status:'h373542, wel:'h0, busy:'h0}, '{other_status:'h21996a, wel:'h0, busy:'h0}}
  UVM_ERROR @ 776927840 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8665aa) != exp '{'{other_status:'h278f2, wel:'h1, busy:'h0}, '{other_status:'h373542, wel:'h1, busy:'h0}, '{other_status:'h21996a, wel:'h0, busy:'h0}, '{other_status:'h373542, wel:'h0, busy:'h0}, '{other_status:'h21996a, wel:'h0, busy:'h0}}
  UVM_ERROR @ 777136180 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8665aa) != exp '{'{other_status:'h278f2, wel:'h1, busy:'h0}, '{other_status:'h373542, wel:'h1, busy:'h0}, '{other_status:'h21996a, wel:'h0, busy:'h0}, '{other_status:'h373542, wel:'h0, busy:'h0}, '{other_status:'h21996a, wel:'h0, busy:'h0}}