SPI_HOST Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.750m	3.201ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	41.065us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	47.337us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	308.704us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	22.583us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	171.120us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	47.337us	20	20	100.00
		spi_host_csr_aliasing	2.000s	22.583us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	35.572us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	23.138us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	3.000s	138.830us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	55.000s	6.096ms	50	50	100.00
		spi_host_error_cmd	2.000s	47.190us	50	50	100.00
		spi_host_event	6.200m	24.919ms	50	50	100.00
V2	clock_rate	spi_host_speed	29.000s	200.000ms	49	50	98.00
V2	speed	spi_host_speed	29.000s	200.000ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	29.000s	200.000ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	3.083m	12.137ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	79.897us	50	50	100.00
V2	cpol_cpha	spi_host_speed	29.000s	200.000ms	49	50	98.00
V2	full_cycle	spi_host_speed	29.000s	200.000ms	49	50	98.00
V2	duplex	spi_host_smoke	1.750m	3.201ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.750m	3.201ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.633m	5.372ms	50	50	100.00
V2	spien	spi_host_spien	1.450m	10.095ms	49	50	98.00
V2	stall	spi_host_status_stall	29.450m	215.853ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	38.000s	7.290ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	55.000s	6.096ms	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	34.078us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	42.668us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	125.496us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	125.496us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	41.065us	5	5	100.00
		spi_host_csr_rw	2.000s	47.337us	20	20	100.00
		spi_host_csr_aliasing	2.000s	22.583us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	79.317us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	41.065us	5	5	100.00
		spi_host_csr_rw	2.000s	47.337us	20	20	100.00
		spi_host_csr_aliasing	2.000s	22.583us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	79.317us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	96.649us	20	20	100.00
		spi_host_sec_cm	2.000s	43.913us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	96.649us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	13.283m	100.017ms	8	10	80.00
		TOTAL			835	840	99.40

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.10	96.82	93.35	98.69	94.35	73.07	100.00	95.21	90.42

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 2.spi_host_upper_range_clkdiv.89752345008566695227120131339396489716505341795373215002499955499274277448975
      Line 112, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_status_stall has 1 failures.

    • 12.spi_host_status_stall.46819065552348917448227553641346366195375031072406161932351266567745954024930
      Line 3224, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_speed has 1 failures.

    • 35.spi_host_speed.45551290526573714999537427516271002781189223677337423591912072753136409221099
      Line 126, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/35.spi_host_speed/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 6.spi_host_upper_range_clkdiv.94436211901957950142550479032318872044973969804927876359734878657047885836905
      Line 131, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100017435967 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0x398489d4, Comparison=CompareOpEq, exp_data=0x0, call_count=11
        UVM_INFO @ 100017435967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_spien has 1 failures.

    • 19.spi_host_spien.32926560739698321208062754198368865321903762609627647226688793311189316746022
      Line 350, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/19.spi_host_spien/latest/run.log

        UVM_FATAL @ 10094730052 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xb20ce494, Comparison=CompareOpEq, exp_data=0x0, call_count=63
        UVM_INFO @ 10094730052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---