SRAM_CTRL/MAIN Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: 2bd4e85

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.887m	5.637ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.100s	22.772us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.110s	150.195us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.180s	129.742us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.080s	27.035us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	18.800s	10.005ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.110s	150.195us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	27.035us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.709m	414.079ms	49	50	98.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.013m	9.833ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	23.764m	43.030ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.970m	10.405ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	38.172m	623.102ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.368m	21.212ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.885m	14.899ms	50	50	100.00
V2	executable	sram_ctrl_executable	20.913m	31.083ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.679m	1.087ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.966m	553.678ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.842m	4.005ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.776m	3.130ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.720m	1.149ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.959m	88.660ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.970s	3.753ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.513h	1.838s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.090s	26.263us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.500s	287.713us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.500s	287.713us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.100s	22.772us	5	5	100.00
		sram_ctrl_csr_rw	1.110s	150.195us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	27.035us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	89.437us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.100s	22.772us	5	5	100.00
		sram_ctrl_csr_rw	1.110s	150.195us	20	20	100.00
		sram_ctrl_csr_aliasing	1.080s	27.035us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	89.437us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.334m	46.933ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.010s	14.397us	0	5	0.00
		sram_ctrl_tl_intg_err	3.850s	434.286us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.010s	14.397us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.850s	434.286us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.959m	88.660ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.959m	88.660ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.110s	150.195us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	20.913m	31.083ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	20.913m	31.083ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	20.913m	31.083ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.885m	14.899ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	9.910s	4.426ms	40	50	80.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.334m	46.933ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.710s	10.957ms	43	50	86.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.887m	5.637ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.887m	5.637ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	20.913m	31.083ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.010s	14.397us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.885m	14.899ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.010s	14.397us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.010s	14.397us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.887m	5.637ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.010s	14.397us	0	5	0.00
V2S		TOTAL			123	145	84.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.166m	10.459ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1166	1190	97.98

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	99.11	92.90	85.46	100.00	98.02	95.83	98.33

Failure Buckets

• Offending 'reqfifo_rvalid' has 10 failures:

  • Test sram_ctrl_mubi_enc_err has 10 failures.

    • 1.sram_ctrl_mubi_enc_err.101085457987643467597712814062100412823117161606033484261989541781853682892512
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2999823273 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2999823273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.sram_ctrl_mubi_enc_err.27295404211637421201176222582707218073099508575240474603585119874837601857200
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2760201079 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2760201079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 7 failures:

  • Test sram_ctrl_readback_err has 7 failures.

    • 11.sram_ctrl_readback_err.55484716608835144417392451744909407740290110468307921953911685221469465751658
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/11.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 678899200 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x62) != exp (0x3b)
        UVM_INFO @ 678899200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 15.sram_ctrl_readback_err.15024131964387111896525546768814470409666857201255319457379921325588974609168
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/15.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1369739429 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5b) != exp (0x3f)
        UVM_INFO @ 1369739429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:

  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.23688287828315425934573721722317668182274964813899043032913907366303723390185
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  17636912 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  17636912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.54788688093872842838265073807267404147267636128208721152286067698282170916818
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7538591 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7538591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '((pend_req[*].pend == *'b0) || $test$plusargs("disable_assert_final_checks"))' has 1 failures:

  • Test sram_ctrl_mem_walk has 1 failures.

    • 0.sram_ctrl_mem_walk.98090886199101853601323031368684797700867237812053223258878435060067543069971
      Line 145, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_walk/latest/run.log

            Offending '((pend_req[161].pend == 1'b0) || $test$plusargs("disable_assert_final_checks"))'
        UVM_ERROR @ 44861535669 ps: (tlul_assert.sv:319) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
        UVM_INFO @ 44861535669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.66869099979181774585271176039924888157217827463271186130861870668270552744171
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3736521 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3736521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 14.sram_ctrl_csr_mem_rw_with_rand_reset.82145363498214391143136657857209985363095102721936456665650022361892809684874
      Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_FATAL @ 10004876737 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
        UVM_INFO @ 10004876737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---