SRAM_CTRL/RET Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: `2bd4e85`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.527m	2.942ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.000s	46.346us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.010s	14.106us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.700s	188.620us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.040s	141.028us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.340s	44.860us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.010s	14.106us	20	20	100.00
		sram_ctrl_csr_aliasing	1.040s	141.028us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.490s	661.429us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.770s	171.268us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	23.145m	21.604ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.450m	4.073ms	49	50	98.00
V2	bijection	sram_ctrl_bijection	1.537m	10.150ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.194m	5.622ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.070s	6.554ms	50	50	100.00
V2	executable	sram_ctrl_executable	22.357m	15.649ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.611m	716.425us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.740m	26.893ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.486m	539.664us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.562m	314.380us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.884m	2.752ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	21.820m	15.485ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.290s	59.052us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.330h	398.660ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.090s	29.862us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.800s	490.378us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.800s	490.378us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.000s	46.346us	5	5	100.00
		sram_ctrl_csr_rw	1.010s	14.106us	20	20	100.00
		sram_ctrl_csr_aliasing	1.040s	141.028us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	145.391us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.000s	46.346us	5	5	100.00
		sram_ctrl_csr_rw	1.010s	14.106us	20	20	100.00
		sram_ctrl_csr_aliasing	1.040s	141.028us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	145.391us	20	20	100.00
V2		TOTAL			789	790	99.87
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.650s	3.910ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.190s	25.226us	0	5	0.00
		sram_ctrl_tl_intg_err	3.410s	514.550us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.190s	25.226us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.410s	514.550us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	21.820m	15.485ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	21.820m	15.485ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.010s	14.106us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	22.357m	15.649ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	22.357m	15.649ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	22.357m	15.649ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.070s	6.554ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.680s	60.508us	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.650s	3.910ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.560s	105.287us	37	50	74.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.527m	2.942ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.527m	2.942ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	22.357m	15.649ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.190s	25.226us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.070s	6.554ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.190s	25.226us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.190s	25.226us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.527m	2.942ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.190s	25.226us	0	5	0.00
V2S		TOTAL			123	145	84.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.941m	8.342ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1164	1190	97.82

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.07	92.90	85.37	100.00	97.98	95.79	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 13 failures:
- Test sram_ctrl_readback_err has 13 failures.
  - 5.sram_ctrl_readback_err.72678682816612433923455946350559022154680544330471258367802228182478706952888
    Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  78989565 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xc) != exp (0x11)
  UVM_INFO @  78989565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.sram_ctrl_readback_err.99691753532947427638219365117254528676121080014441673788342882810461607703899
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  84004012 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0x35)
  UVM_INFO @  84004012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
Offending 'reqfifo_rvalid' has 3 failures:
- Test sram_ctrl_mubi_enc_err has 3 failures.
  - 3.sram_ctrl_mubi_enc_err.88737810801587243028714339084876598174223746077483229741243667270676915700519
    Line 106, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  23593614 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  23593614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.sram_ctrl_mubi_enc_err.107834692766962525044615805555088737174739652393776577352532982176752612287535
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 212642905 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 212642905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

1.sram_ctrl_sec_cm.40412709588097270832065081102953943751272616322333733096851442636883835196760
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   9574661 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   9574661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sram_ctrl_sec_cm.24727151841843630017633984842928298573250950337831929692363599730879074759962
Line 102, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   5073642 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   5073642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(depth_o <= *'(Depth))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 0.sram_ctrl_sec_cm.98962020761387983559172024651177960092954070740515661615845122745016570878208
    Line 103, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   1252454 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   1252454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.37753630105853778056169129943400985198677519690746889017641144533434906661902
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 212806857 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 212806857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test sram_ctrl_sec_cm has 1 failures.

2.sram_ctrl_sec_cm.17202960173501577537168417707870156128574799932068884602870038026952463331233
Line 103, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv", 211: tb.dut.u_tlul_adapter_sram_racl.tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth: started at 1033827ps failed at 1033827ps
      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   1033827 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   1033827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 3.sram_ctrl_sec_cm.80542705121401994668108870175322857853100218427297600798966572033795910657938
    Line 103, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  25226208 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  25226208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 8.sram_ctrl_csr_mem_rw_with_rand_reset.34941981315945549107454252894896873577317750753103771331111901898914992405935
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 142842042 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @ 142842042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3800) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

9.sram_ctrl_mubi_enc_err.71773540617596022888451093980464263260495029118442043348811267440977335464413
Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @ 285256899 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3800) { a_addr: 'h16dd2288  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h2652a  d_param: 'h0  d_source: 'h13  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 285256899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job returned non-zero exit code has 1 failures:

Test sram_ctrl_stress_pipeline has 1 failures.

15.sram_ctrl_stress_pipeline.43045925855843868756151139995306466030066874469859347517910921271775878393380
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_pipeline/latest/run.log

  Chronologic VCS simulator copyright 1991-2023
  Contains Synopsys proprietary information.
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  Please contact VCS Customer Support at 1-800-VERILOG for more information.

  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255

UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 16.sram_ctrl_stress_all_with_rand_reset.87647249268386366685663437150856606597253317455194520534604564452308527063091
    Line 497, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5324195159 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5324195159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```