2bd4e85| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 55.300s | 11.093ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | uart_csr_hw_reset | 0.960s | 25.759us | 5 | 5 | 100.00 |
| V1 | csr_rw | uart_csr_rw | 0.990s | 16.030us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | uart_csr_bit_bash | 2.740s | 559.881us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | uart_csr_aliasing | 1.130s | 29.228us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 1.290s | 23.653us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0.990s | 16.030us | 20 | 20 | 100.00 |
| uart_csr_aliasing | 1.130s | 29.228us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | base_random_seq | uart_tx_rx | 4.396m | 126.708ms | 50 | 50 | 100.00 |
| V2 | parity | uart_smoke | 55.300s | 11.093ms | 50 | 50 | 100.00 |
| uart_tx_rx | 4.396m | 126.708ms | 50 | 50 | 100.00 | ||
| V2 | parity_error | uart_intr | 7.476m | 267.489ms | 50 | 50 | 100.00 |
| uart_rx_parity_err | 3.307m | 81.066ms | 50 | 50 | 100.00 | ||
| V2 | watermark | uart_tx_rx | 4.396m | 126.708ms | 50 | 50 | 100.00 |
| uart_intr | 7.476m | 267.489ms | 50 | 50 | 100.00 | ||
| V2 | fifo_full | uart_fifo_full | 7.480m | 207.654ms | 50 | 50 | 100.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 10.550m | 329.740ms | 50 | 50 | 100.00 |
| V2 | fifo_reset | uart_fifo_reset | 7.476m | 156.834ms | 300 | 300 | 100.00 |
| V2 | rx_frame_err | uart_intr | 7.476m | 267.489ms | 50 | 50 | 100.00 |
| V2 | rx_break_err | uart_intr | 7.476m | 267.489ms | 50 | 50 | 100.00 |
| V2 | rx_timeout | uart_intr | 7.476m | 267.489ms | 50 | 50 | 100.00 |
| V2 | perf | uart_perf | 22.099m | 28.421ms | 49 | 50 | 98.00 |
| V2 | sys_loopback | uart_loopback | 20.720s | 11.642ms | 50 | 50 | 100.00 |
| V2 | line_loopback | uart_loopback | 20.720s | 11.642ms | 50 | 50 | 100.00 |
| V2 | rx_noise_filter | uart_noise_filter | 2.165m | 186.235ms | 7 | 50 | 14.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 47.970s | 32.296ms | 50 | 50 | 100.00 |
| V2 | tx_overide | uart_tx_ovrd | 24.120s | 6.302ms | 50 | 50 | 100.00 |
| V2 | rx_oversample | uart_rx_oversample | 57.470s | 6.086ms | 50 | 50 | 100.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 17.862m | 196.187ms | 49 | 50 | 98.00 |
| V2 | stress_all | uart_stress_all | 18.547m | 432.704ms | 40 | 50 | 80.00 |
| V2 | alert_test | uart_alert_test | 0.950s | 23.179us | 50 | 50 | 100.00 |
| V2 | intr_test | uart_intr_test | 0.950s | 18.755us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 2.600s | 116.675us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | uart_tl_errors | 2.600s | 116.675us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0.960s | 25.759us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.990s | 16.030us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 1.130s | 29.228us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 1.100s | 62.681us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 0.960s | 25.759us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.990s | 16.030us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 1.130s | 29.228us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 1.100s | 62.681us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1035 | 1090 | 94.95 | |||
| V2S | tl_intg_err | uart_sec_cm | 1.280s | 65.820us | 5 | 5 | 100.00 |
| uart_tl_intg_err | 1.770s | 177.801us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 1.770s | 177.801us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | uart_stress_all_with_rand_reset | 1.806m | 22.735ms | 87 | 100 | 87.00 |
| V3 | TOTAL | 87 | 100 | 87.00 | |||
| TOTAL | 1252 | 1320 | 94.85 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 94.53 | 99.48 | 98.25 | 74.67 | -- | 98.14 | 97.12 | 99.55 |
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 24 failures:
1.uart_noise_filter.37622237416846646230704972288015347704634187026118354172688260035276640295071
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log
UVM_ERROR @ 4030651 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4030651 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 299950651 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 299960651 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 299970651 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (134 [0x86] vs 255 [0xff]) reg name: uart_reg_block.rdata
2.uart_noise_filter.90831417979129764295041797490610770094464700865003869330638352070412547052444
Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log
UVM_ERROR @ 31367918595 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 31488252891 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 31488294558 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 31488336225 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 31534628262 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
... and 15 more failures.
17.uart_stress_all_with_rand_reset.103381934305509386566623168811246466490529521944432551898633629489111512264393
Line 136, in log /nightly/current_run/scratch/master/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8078585175 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8079632793 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8082680409 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8083442313 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8084966121 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
25.uart_stress_all_with_rand_reset.54575243407300587615119143732471527958910417958501337981978203941376427191885
Line 95, in log /nightly/current_run/scratch/master/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4254224058 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4254224058 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 4452933981 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/40
UVM_ERROR @ 4735811244 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 7
UVM_ERROR @ 4735852911 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
... and 4 more failures.
22.uart_stress_all.108086193227647606043500380787170051713002345231204403991062004827534807294500
Line 77, in log /nightly/current_run/scratch/master/uart-sim-vcs/22.uart_stress_all/latest/run.log
UVM_ERROR @ 6725133703 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6725133703 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 6850728743 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6851029827 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6851384676 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 21 failures:
0.uart_noise_filter.80628570455390235746525476796953148097549061885933550051731980247338678770201
Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log
UVM_ERROR @ 32578360252 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5, clk_pulses: 0
UVM_ERROR @ 32578381085 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 32578401918 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 32793502643 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7, clk_pulses: 0
UVM_ERROR @ 32793523476 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
3.uart_noise_filter.79210394715708356498685081218467262002027745011363762282932713568190392615414
Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/3.uart_noise_filter/latest/run.log
UVM_ERROR @ 6823368741 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 8, clk_pulses: 0
UVM_ERROR @ 6823389574 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6823556238 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (189 [0xbd] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 6823577071 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6823660403 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (189 [0xbd] vs 247 [0xf7]) reg name: uart_reg_block.rdata
... and 9 more failures.
10.uart_stress_all.71409974003690958000748630293642624658244567094277577511111584045770500998115
Line 78, in log /nightly/current_run/scratch/master/uart-sim-vcs/10.uart_stress_all/latest/run.log
UVM_ERROR @ 18101187837 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 18101212227 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 18101382957 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 18219064707 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 18219064707 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
12.uart_stress_all.21623907250804554675213171783118216097249473646769766715849815957021063354509
Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/12.uart_stress_all/latest/run.log
UVM_ERROR @ 7751787484 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 7751829151 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 7751870818 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (44 [0x2c] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 8166124132 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5, clk_pulses: 0
UVM_ERROR @ 8166165799 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
... and 5 more failures.
51.uart_stress_all_with_rand_reset.40866855213588296906027726111750828991155535755415867634511872039432347905859
Line 170, in log /nightly/current_run/scratch/master/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3375701107 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 3375711524 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 3375721941 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 3375732358 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 3375742775 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
74.uart_stress_all_with_rand_reset.42567955484038684060184973241466921348929295641474208910763191539998015525525
Line 96, in log /nightly/current_run/scratch/master/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1947135432 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 1947155840 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1947176248 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_INFO @ 1953747624 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/878
UVM_ERROR @ 2029196000 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
... and 1 more failures.
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 14 failures:
Test uart_noise_filter has 10 failures.
8.uart_noise_filter.102914143299069183159776231556857272141665308797932430364004013201041754103456
Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log
UVM_ERROR @ 4071608378 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 4071608378 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4071608378 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 4102758378 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 4
UVM_ERROR @ 4102768378 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
13.uart_noise_filter.70198623719134233080523737560443624179707567896202596862917901301846538346750
Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/13.uart_noise_filter/latest/run.log
UVM_ERROR @ 58104518757 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 58104518757 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 58118185533 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 58118185533 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 58118185533 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
... and 8 more failures.
Test uart_long_xfer_wo_dly has 1 failures.
11.uart_long_xfer_wo_dly.32560036640548473995921514646473774335201561089754512815304421595475069549197
Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest/run.log
UVM_ERROR @ 14944959072 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_INFO @ 21133655640 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/7
UVM_INFO @ 55724520600 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 5/7
UVM_ERROR @ 59051664864 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_INFO @ 61034151312 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 6/7
Test uart_stress_all has 1 failures.
27.uart_stress_all.4288192248799675546863953407961966386559740437110023827018317885473795079862
Line 89, in log /nightly/current_run/scratch/master/uart-sim-vcs/27.uart_stress_all/latest/run.log
UVM_ERROR @ 70742816850 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 70742816850 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 70742816850 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 70787946850 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 71010896850 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
Test uart_stress_all_with_rand_reset has 2 failures.
34.uart_stress_all_with_rand_reset.24908593583287795236543649612527132253769992452800457161187699810064529304374
Line 174, in log /nightly/current_run/scratch/master/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2671805939 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 2671805939 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2671805939 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 2674535193 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/125
UVM_ERROR @ 2699817252 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 4
90.uart_stress_all_with_rand_reset.27469786854432642829794955992744135240605733000817177593814915469538181483545
Line 121, in log /nightly/current_run/scratch/master/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3939204490 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 3939204490 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3939204490 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 3989435209 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/429
UVM_ERROR @ 4151742739 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 5 failures:
6.uart_noise_filter.83650924599075321529156574760781329704814901532009611672637878908710032697121
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/6.uart_noise_filter/latest/run.log
UVM_ERROR @ 96370353 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 96370353 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 96474518 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 96474518 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 99078643 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
15.uart_noise_filter.73534640160790222692336623701678853042396248967244394875798699013366713739854
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/15.uart_noise_filter/latest/run.log
UVM_ERROR @ 193119808 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 306679808 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 306679808 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 310879808 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 312099808 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
... and 3 more failures.
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 2 failures:
Test uart_stress_all has 1 failures.
2.uart_stress_all.111397983216650598171441344448972956925194050408148665541610050138928031775767
Line 92, in log /nightly/current_run/scratch/master/uart-sim-vcs/2.uart_stress_all/latest/run.log
UVM_ERROR @ 143774440031 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 145932590031 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/6
UVM_INFO @ 147330240031 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/6
UVM_INFO @ 147569590031 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/6
UVM_INFO @ 147959240031 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/6
Test uart_perf has 1 failures.
23.uart_perf.58601237490789398322681870505827598081737830487752913446054250965417506193694
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/23.uart_perf/latest/run.log
UVM_ERROR @ 1976049 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 942523657 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/7
UVM_INFO @ 4301764633 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/7
UVM_INFO @ 8742336201 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/7
UVM_INFO @ 8785668841 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/7
UVM_ERROR (cip_base_vseq.sv:1229) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
4.uart_stress_all_with_rand_reset.100232278493555552882845694173162430729195854998532492133691133304251245962875
Line 86, in log /nightly/current_run/scratch/master/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 497080419 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 497084751 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 497084751 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 497090945 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 1 failures:
69.uart_stress_all_with_rand_reset.54868841236568882843671080514106433406810718571627280930326647871120701376117
Line 123, in log /nightly/current_run/scratch/master/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4048475913 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 4048475913 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
UVM_INFO @ 4066308961 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/313
UVM_ERROR @ 4085433655 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 4085433655 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark