CHIP Simulation Results

Friday October 24 2025 17:04:32 UTC

GitHub Revision: `2bd4e85`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.906m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.906m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.666m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	2.190m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	2.178m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.937m	4.785ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.937m	4.785ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.937m	4.785ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	37.450s	10.120us	0	3	0.00
		chip_sw_example_manufacturer	2.795m		0	3	0.00
		chip_sw_example_concurrency	6.457m	5.241ms	3	3	100.00
		chip_sw_uart_smoketest_signed	18.948s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	14.600s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	13.990s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	13.990s		0	3	0.00
V1	xbar_smoke	xbar_smoke	37.210s	70.692us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.239m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.946m	8.208ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	6.385m	5.699ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.354m		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.585m		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	2.020m		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.810m		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.550s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.550s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.434m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.526m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.523m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.523m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.639m	3.452ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	4.542m	4.994ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	10.499m	10.118ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	16.711s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	18.033s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	17.777m	14.988ms	1	3	33.33
V2	chip_sw_timer	chip_sw_rv_timer_irq	8.483m	6.067ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	38.063m	18.019ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	38.063m	18.019ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	18.639s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.631m	5.576ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.631m	5.576ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	11.358m	18.019ms	0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.902m	4.902ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.534m	6.071ms	3	3	100.00
		chip_sw_aes_idle	6.282m	5.456ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.393m	5.820ms	3	3	100.00
		chip_sw_kmac_idle	5.636m	3.813ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	21.123m	12.018ms	0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	19.945m	12.027ms	0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	20.610m	12.019ms	0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	20.117m	11.999ms	1	3	33.33
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	19.324s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.971s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.871s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.463s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.141s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.894s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.945s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	19.324s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.971s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.871s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.463s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.141s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.894s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.945s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	19.137s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.017m	10.160us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.197m	10.100us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.240s	10.180us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.160s	10.400us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	23.391s		0	3	0.00
		chip_sw_clkmgr_jitter	6.093m	4.752ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.617m	3.847ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	17.141s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.110m	10.180us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	49.260s	10.180us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1.045m	10.200us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.001m	10.180us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.025m	10.340us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	18.158s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	17.783s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	18.633s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	19.232s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	35.680m	15.696ms	83	100	83.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	16.640m	16.164ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	7.631m	5.576ms	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	19.895s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	16.640m	16.164ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	17.777s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	36.865s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	56.729s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	25.981s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	18.146s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	35.680m	15.696ms	83	100	83.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	10.499m	10.118ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	41.899m	20.018ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.007m	5.556ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.346m	10.676ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.998m	4.781ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	35.680m	15.696ms	83	100	83.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	18.753s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	23.264s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	35.680m	15.696ms	83	100	83.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	19.066s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.346m	10.676ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	19.144s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	27.405s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	17.943s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.432s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	19.315s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	19.776s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	23.264s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	1.068m		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.397m		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	1.068m		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	1.068m		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	1.068m		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	12.298m	9.207ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	48.453s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	55.986s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	1.006m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	42.708s		0	3	0.00
		chip_sw_lc_ctrl_transition	1.068m		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	11.123m	10.514ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	15.878m	12.597ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	21.585s		0	3	0.00
		chip_prim_tl_access	16.307m	18.139ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	19.324s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.971s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.871s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.463s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.141s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.894s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.945s		0	3	0.00
		chip_rv_dm_lc_disabled	17.777m	14.988ms	1	3	33.33
V2	chip_sw_aes_enc	chip_sw_aes_enc	7.946m	5.529ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	1.017m	10.160us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.762m	3.570ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	6.282m	5.456ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.697m	5.447ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	1.197m	10.100us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.393m	5.820ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.581m	3.789ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.986m	5.613ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	49.160s	10.400us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	11.123m	10.514ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	1.068m		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	52.660s	10.100us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	7.534m	5.588ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.636m	3.813ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	17.768s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	17.768s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	19.283s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.756m	5.969ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	19.188s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	11.123m	10.514ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.240s	10.180us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	18.218s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	19.137s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.534m	6.071ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.534m	6.071ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.534m	6.071ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	11.679m	5.448ms	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	15.878m	12.597ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	15.878m	12.597ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.319m	10.810ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	23.391s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	21.585s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	35.680m	15.696ms	83	100	83.00
		chip_sw_data_integrity_escalation	2.523m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	1.068m		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	11.679m	5.448ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	11.123m	10.514ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	12.319m	10.810ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.001m	4.790ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	11.679m	5.448ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	11.123m	10.514ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	12.319m	10.810ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.001m	4.790ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	1.068m		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	19.780s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.397m		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	48.453s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	55.986s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	1.006m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	42.708s		0	3	0.00
		chip_sw_lc_ctrl_transition	1.068m		0	15	0.00
		chip_prim_tl_access	16.307m	18.139ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	16.307m	18.139ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.804s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	17.728s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	17.783s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	19.137s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.017m	10.160us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.197m	10.100us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.240s	10.180us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.160s	10.400us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	23.391s		0	3	0.00
		chip_sw_clkmgr_jitter	6.093m	4.752ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	10.092m	6.311ms	2	3	66.67
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	10.092m	6.311ms	2	3	66.67
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	6.797m	3.685ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.651m	4.235ms	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.877m	5.014ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	10.331m	5.281ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.835m	6.069ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.902m	4.005ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	6.001m	4.790ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	41.899m	20.018ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	41.899m	20.018ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	5.521m	4.246ms	3	3	100.00
		chip_sw_aon_timer_smoketest	7.036m	4.731ms	3	3	100.00
		chip_sw_clkmgr_smoketest	6.673m	5.281ms	3	3	100.00
		chip_sw_csrng_smoketest	7.152m	4.898ms	3	3	100.00
		chip_sw_gpio_smoketest	8.057m	5.886ms	3	3	100.00
		chip_sw_hmac_smoketest	6.564m	3.985ms	3	3	100.00
		chip_sw_kmac_smoketest	7.372m	5.677ms	3	3	100.00
		chip_sw_otbn_smoketest	8.454m	5.883ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.955m	5.432ms	3	3	100.00
		chip_sw_rv_plic_smoketest	6.014m	5.130ms	3	3	100.00
		chip_sw_rv_timer_smoketest	8.796m	6.366ms	3	3	100.00
		chip_sw_rstmgr_smoketest	6.094m	5.518ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.947m	4.234ms	3	3	100.00
		chip_sw_uart_smoketest	6.616m	5.809ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	22.023s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	18.948s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.239m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	19.121s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.544m	4.676ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.262m	3.803ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.094m	5.541ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.183m	6.273ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	25.709s		0	3	0.00
		chip_rv_dm_lc_disabled	17.777m	14.988ms	1	3	33.33
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.279m		0	3	0.00
		chip_sw_lc_walkthrough_prod	37.065s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	46.316s		0	3	0.00
		chip_sw_lc_walkthrough_rma	1.394m		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	25.709s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	10.903m	8.755ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	9.663m	8.589ms	3	3	100.00
		rom_volatile_raw_unlock	17.607s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	20.189s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.453m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.431m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	5.936m	5.079ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	5.936m	5.079ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	13.990s		0	3	0.00
		chip_same_csr_outstanding	12.990s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	13.990s		0	3	0.00
		chip_same_csr_outstanding	12.990s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	4.667m	520.145us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	16.780s	13.355us	100	100	100.00
		xbar_smoke_large_delays	8.656m	3.009ms	100	100	100.00
		xbar_smoke_slow_rsp	10.570m	2.204ms	100	100	100.00
		xbar_random_zero_delays	2.323m	75.657us	100	100	100.00
		xbar_random_large_delays	32.381m	12.920ms	100	100	100.00
		xbar_random_slow_rsp	51.575m	14.510ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.760m	204.869us	100	100	100.00
		xbar_error_and_unmapped_addr	2.822m	244.560us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	5.115m	499.881us	100	100	100.00
		xbar_error_and_unmapped_addr	2.822m	244.560us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	7.887m	818.404us	100	100	100.00
		xbar_access_same_device_slow_rsp	58.081m	19.143ms	78	100	78.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	4.018m	452.255us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	30.579m	4.042ms	100	100	100.00
		xbar_stress_all_with_error	46.102m	5.829ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	54.826m	4.794ms	97	100	97.00
		xbar_stress_all_with_reset_error	58.246m	7.443ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	19.358s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	18.970s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	17.484s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	16.631s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	16.835s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	13.192s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	16.674s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	18.135s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	15.709s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.879s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	15.874s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	13.046s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.887s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	35.265s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	33.958s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	35.514s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	35.843s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	29.062s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	29.370s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	53.236s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	54.481s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	51.145s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	55.920s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	54.100s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	54.885s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	53.265s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	46.509s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	46.779s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	18.215s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.273s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.899s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.182s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.604s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	19.108s		0	3	0.00
		rom_e2e_asm_init_dev	18.715s		0	3	0.00
		rom_e2e_asm_init_prod	18.432s		0	3	0.00
		rom_e2e_asm_init_prod_end	19.667s		0	3	0.00
		rom_e2e_asm_init_rma	19.350s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	18.810s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	19.463s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	17.691s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	19.179s		0	3	0.00
V2		TOTAL			1900	2429	78.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.400m	5.920ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.978m	5.023ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.077s		0	1	0.00
		rom_e2e_jtag_debug_dev	16.106s		0	1	0.00
		rom_e2e_jtag_debug_rma	16.158s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	17.615s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	35.680m	15.696ms	83	100	83.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	27.125s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.684m	5.734ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	17.790s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	19.659s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.077s		0	1	0.00
		rom_e2e_jtag_debug_dev	16.106s		0	1	0.00
		rom_e2e_jtag_debug_rma	16.158s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	13.829s		0	1	0.00
		rom_e2e_jtag_inject_dev	15.492s		0	1	0.00
		rom_e2e_jtag_inject_rma	17.472s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	18.462s		0	3	0.00
V3		TOTAL			0	20	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	30.791m	17.200ms	3	3	100.00
		chip_sw_entropy_src_kat_test	6.737m	5.746ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	6.562m	5.099ms	3	3	100.00
		chip_plic_all_irqs_0	14.310m	7.702ms	3	3	100.00
		chip_plic_all_irqs_10	15.274m	6.670ms	3	3	100.00
		chip_sw_dma_inline_hashing	7.460m	5.906ms	3	3	100.00
		chip_sw_dma_abort	7.366m	6.074ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	19.520s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	19.458s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	19.305s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	18.556s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	17.848s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	18.518s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	19.129s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	19.371s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	18.254s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	18.995s		0	3	0.00
		chip_sw_entropy_src_smoketest	8.544m	5.830ms	3	3	100.00
		chip_sw_mbx_smoketest	7.936m	5.141ms	3	3	100.00
		TOTAL			2036	2668	76.31

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
72.88	73.94	78.23	64.37	57.14	81.00	68.62	86.89

Failure Buckets

Job returned non-zero exit code has 449 failures:

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.49910959797736136086616438407268521796466569063597145491252316545518727047073
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 150.709s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_manufacturer.54149626498426522243001218183770656002037900917660086433206559083183723677282
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 1.739s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_data_integrity_escalation has 6 failures.

0.chip_sw_data_integrity_escalation.19017992643256806360124192035307904936310784747435946019387158347840621278015
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 133.756s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_data_integrity_escalation.82071037610818462172401586310516549855902722421995989773100902915684762110202
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 2.172s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 4 more failures.

Test chip_sw_sleep_pin_wake has 3 failures.

0.chip_sw_sleep_pin_wake.10960313739021845381319790010347762189615099244680466671963462816837943672218
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.226s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_wake.80448339795190629499438877399501833801822281761647490859157196193920129415350
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 38.747s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_sleep_pin_retention has 3 failures.

0.chip_sw_sleep_pin_retention.82609800168488130971760739344877375868325149910528179728268863956731122169997
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 135.191s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_retention.91805785039888446942626071922001083744776554463154872481213246586106511169079
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 4.774s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_uart_tx_rx has 5 failures.

0.chip_sw_uart_tx_rx.37316166800529983607575258415708331642570589557033814252249553428258283358256
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 159.619s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_uart_tx_rx.3694507336532273286483791889844531265680088256603217240416375416999389365386
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 18.235s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 3 more failures.

... and 129 more tests.

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 30 failures:
- Test chip_tl_errors has 30 failures.
  - 0.chip_tl_errors.24171380215022881806367054438277145317876825962854343805074577261587971907281
    Line 237, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4395.247732 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4395.247732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_tl_errors.100178163951285919080580097215973426776850144841248673379216201618570697581108
    Line 237, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3203.811452 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3203.811452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 28 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:
- Test chip_sw_aes_enc_jitter_en has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en.73373226197375601145632556269917851483717219004205460198138051971169648508734
    Line 449, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en.72284861702025698265755037881283014207837817975296715412241003117592999872458
    Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_hmac_enc_jitter_en has 3 failures.
  - 0.chip_sw_hmac_enc_jitter_en.86483379568373934324209365590119350261074231294856943467714990931766489056140
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_enc_jitter_en.68731427028633254898864109604178265097426910096307451929245014952132880954944
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.21228004021401522649009772134312417913530147664752714929991774090181061555725
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.52205662490456813953418255249575815003764905873398957357068013881159061742864
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.63306562289772475681974514074540926710973273311088056741395398019129997387
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_mode_kmac_jitter_en.31615370974360232825928673659727370833231544954862070812369214480226626406135
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.42441956476260036662583204313294088637702726449942717497427455256452235828939
    Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en_reduced_freq.13179324910090056383429205181859189843174929515213265366933079083176147692261
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 4 more tests.
Job timed out after * minutes has 25 failures:
- Test xbar_access_same_device_slow_rsp has 22 failures.
  - 0.xbar_access_same_device_slow_rsp.4419443084249768070580685540586770385238384750149284945321441413858777240902
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.xbar_access_same_device_slow_rsp.32499209179580945890859967189693921466829480889003702331080937990405135337618
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 20 more failures.
- Test xbar_stress_all_with_rand_reset has 3 failures.
  - 4.xbar_stress_all_with_rand_reset.60645506020453072571326490049050111687111874497454346519477884624476311095262
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - 52.xbar_stress_all_with_rand_reset.53412858312181859970990155636555244673560658763202136751677677545262374833684
    Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 13 failures:

Test chip_sw_rstmgr_cpu_info has 3 failures.

0.chip_sw_rstmgr_cpu_info.14918880934941011897106766447134402635072899590654037155724785379897509722747
Line 555, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.472052 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.472052 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_cpu_info.11156134804373126663686796620109536395961709058658793259991802353021931517261
Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.673129 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.673129 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_irq has 3 failures.

0.chip_sw_aon_timer_irq.66363537516037422815131169594723997382291952089867027539810913411393336293408
Line 488, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.823695 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.823695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_irq.110798966601408392980076393568168715730960200636781036934408060283430230580014
Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.588221 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.588221 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 5 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.103102569013353115474819425030509646759046917182000566726551248915453395785338
Line 507, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.454971 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.454971 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_sleep_wdog_sleep_pause.67433817925861002555903783692807899559229643017349085818580578498565074406100
Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.458999 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.458999 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test chip_sw_clkmgr_off_hmac_trans has 2 failures.

1.chip_sw_clkmgr_off_hmac_trans.14136821982715785648979789578035155083963624913448988461520583785923200427216
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.430414 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.430414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_clkmgr_off_hmac_trans.70966543116002037947912579544975407687783772560465018783559637369743030551208
Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.908189 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.908189 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
- Test chip_padctrl_attributes has 10 failures.
  - 0.chip_padctrl_attributes.47269021755139663819980838555709025304692887018535031506839778620078016680598
    Line 283, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.chip_padctrl_attributes.70489180695629945410959757915513807895826368328426322536857400581052817124669
    Line 283, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.24649067599685775650159448725230218956963688979870503020548950049952004015312
    Line 138, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.18690863623011118781923946605955053863401060627118590302722233229501291610191
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.52459281454022494679051138481113688719464223646950449956550931845812447930775
    Line 138, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.111430458522480347526755017429351206854657743373259638017995595194069904968062
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.100011743013128983332488236913926755916405537184296344315142872981412845567207
    Line 138, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.106727651441388068940595192611389798904660020556534102432657245053578249440899
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 9 failures:

Test chip_sw_clkmgr_off_aes_trans has 3 failures.

0.chip_sw_clkmgr_off_aes_trans.66066295566268238098802988673425979651338583031146821658115338896653544282424
Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.469593 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.469593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_aes_trans.12739701130822892499083192889610604624928787156139361848606015185850373760304
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.402439 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.402439 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.49473758647288660148209609826639616025754087918674856186757973388577287711824
Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.695966 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.695966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 3 failures.

0.chip_sw_clkmgr_off_kmac_trans.74852057436973149362784807197997486150862733266248352185080626161851514594120
Line 418, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.431128 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.431128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_kmac_trans.84327652634257747799325910117260402902792201877334847231403461552253559568345
Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.641059 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.641059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_clkmgr_off_otbn_trans has 2 failures.

0.chip_sw_clkmgr_off_otbn_trans.13911034126103916954076607973416029803437230388363992450501434813273069439854
Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.736145 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.736145 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_off_otbn_trans.80824402097207989335708057627345022588655865727297943806608714706064510499085
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12018.506608 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.506608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 6 failures:

Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation.29737902828582778942909019821278994687153471688276459459373425056829092266001
Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 5819.583650 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11622061356446612110540805622396623123991075676097088815197294825187551700640965562015211941933273451936177929392749121882116037904019314979354521203203164 [0xdde773dbaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35bb1c32a7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 5819.583650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation.26902433432345420547624404328148431662398466245912755634025959584967510032008
Line 442, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 10513.682990 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (10462902353839002102694617485725331746963337277619773908085158598818335546239717080237925390123726829657869854666057670245040209787586918527099742118567004 [0xc7c599f4aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3419329057f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 10513.682990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.26832375614085483091353284647721427212224097425542654633144815054217635317654
Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7212.087820 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (12877477115561311699951518385161081060422844952363282253027983106884154715827685939092743963471893570978807627855121578508809635306269166657533370171743324 [0xf5dfcc06aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd373897cf77f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 7212.087820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation_prod.9856183873146222814714969350916860368363751578468753563936765373535723784857
Line 427, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7133.693977 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (3700811774246023238947737943880598579202512614196649128795687455879730668572248345421753604032559325284248420235030340704763624087873666460282057927253084 [0x46a930eeaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3c0ff801f7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 7133.693977 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

Test chip_jtag_csr_rw has 3 failures.

0.chip_jtag_csr_rw.87633632389701047733673023902670816622344735542431507393357471942578462962275
Line 6267, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5084.984440 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'hec332cf7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h26969  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5084.984440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_csr_rw.34873934897180074390379513380873097738791077204579739364795939117637975555881
Line 6267, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3451.595988 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'hf3480d07  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h1  a_user: 'h248c9  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3451.595988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_jtag_mem_access has 3 failures.

0.chip_jtag_mem_access.29930554242910010799711297396525567130108717568792533189439564739390364619020
Line 6267, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4993.963930 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h67866a7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h1  a_user: 'h248d9  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4993.963930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_mem_access.58769262696959937366020331596624406632653312167317179343194059869171418194246
Line 6267, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4518.303151 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'hb07aa9e7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h2692f  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4518.303151 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 6 failures:
- Test chip_sw_all_escalation_resets has 6 failures.
  - 3.chip_sw_all_escalation_resets.96367567507629679929601465547256707474177765973022018659124513311398358174363
    Line 419, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.320001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.chip_sw_all_escalation_resets.79003608830102274851226830928903150688559322474168496678396677269190433337649
    Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.380001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 6 failures:
- Test chip_sw_all_escalation_resets has 6 failures.
  - 52.chip_sw_all_escalation_resets.55546700083630820790024632809605137247194630616992074360321661062825449332273
    Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 4653.117516 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
  UVM_INFO @ 4653.117516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 60.chip_sw_all_escalation_resets.27126141105885189214377887757075706692665130762207290436811855562911747316255
    Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 5519.532852 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
  UVM_INFO @ 5519.532852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 4 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.43291555847030565901028604364100483280600774497863983553799826381700612410124
    Line 459, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 5734.040118 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 5734.040118 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_all_escalation_resets has 3 failures.
  - 16.chip_sw_all_escalation_resets.99703521143024860022440869832218800718177926401816118058169357060678337635676
    Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3934.502656 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3934.502656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 31.chip_sw_all_escalation_resets.31520663567102146675586514901869917200117646607694455970862203632861973902328
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 4993.918478 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 4993.918478 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_example_rom has 3 failures.
  - 0.chip_sw_example_rom.26653392129448961804539339441306128966772364343497234727001717537544226304580
    Line 1380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_example_rom.113093247743450974568586575400227236392893348909518152130627126410226547913444
    Line 379, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.47098910797517726887150422467883238443130685980274150925920625984394081849736
    Line 476, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3546.451927 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3546.451927 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.81154049716493020561469513882605564010396317883407819858623015722930743865042
    Line 453, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5698.612840 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5698.612840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 3 failures:
- Test chip_sw_rstmgr_alert_info has 3 failures.
  - 0.chip_sw_rstmgr_alert_info.26784695533972027182917539165964008935944814550103144634412113274823391774478
    Line 694, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10538.984080 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10538.984080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rstmgr_alert_info.10344773688031904277776665740483324995778765607210320080444643767573760649829
    Line 635, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6635.958250 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6635.958250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

Test chip_sw_soc_proxy_external_alerts has 3 failures.

0.chip_sw_soc_proxy_external_alerts.102529449560902809374755360454971434138946791849523065661482059353709775686905
Line 487, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 5205.164252 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5205.164252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_soc_proxy_external_alerts.3007283825193057378643916487512747184129016751361319403542974931193379743654
Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 3684.578450 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3684.578450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
- Test chip_sw_soc_proxy_external_wakeup has 3 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.15668153838098845027866406278230201754758527662101099700715731178234222964612
    Line 437, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4234.987858 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4234.987858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_soc_proxy_external_wakeup.108909947233927301085773910948381227583328087291576903984462594624145471687655
    Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3755.084670 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3755.084670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.74330094415375510231144450692240309289767945422148823581052825361606231239666
    Line 422, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4096.759612 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4096.759612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aon_timer_wdog_bite_reset.44348801239026143508969428992314528636564950260738311571710035385938566635500
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5156.726800 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5156.726800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.23786156740504814705885381738934815212909423314695784533376606525612996230187
    Line 466, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4784.229212 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4784.229212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.87423360378131081143873991516511412816321747604399075436540589321567262914112
    Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6238.414560 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6238.414560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_kmac_app_rom has 3 failures.
  - 0.chip_sw_kmac_app_rom.111574660399517612194863830868299840561045881723453723575067563451718582389835
    Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_app_rom.40635693527908258729668815041049168739440270809370748434828949092987467203243
    Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

Test chip_sw_dma_abort has 3 failures.

0.chip_sw_dma_abort.100932853596636726007123718765281379642031905926660930097468215673222714194882
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4203.840648 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4203.840648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_dma_abort.66339528839403359957816533764633126310115565046198393332299114831912817905936
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4401.254046 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4401.254046 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:

Test chip_rv_dm_lc_disabled has 2 failures.

0.chip_rv_dm_lc_disabled.23195411451067132658809219847812842288263032604686352913894542023926557049738
Line 237, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 13586.670013 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40408 read out mismatch
  UVM_INFO @ 13586.670013 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_rv_dm_lc_disabled.2627973703275182001399223001380890515954139726503238945784848058159452199156
Line 237, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 8952.141640 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x4053c read out mismatch
  UVM_INFO @ 8952.141640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:

Test chip_sw_all_escalation_resets has 2 failures.

4.chip_sw_all_escalation_resets.98928925993298477228978701264284957844636423102022746569818124805721393122977
Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 12026.974261 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.974261 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.chip_sw_all_escalation_resets.53515426705276584779038390056220456852284223105412161404472442142039883457479
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 12026.664951 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.664951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:52) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! has 1 failures:
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.49013477635200940835011265643562274901040348855793408673926327000169077251707
    Line 514, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 3638.412000 us: (chip_sw_soc_proxy_smoke_vseq.sv:52) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
  UVM_INFO @ 3638.412000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```