AES/MASKED Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: `d00a6c8`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	78.731us	1	1	100.00
V1	smoke	aes_smoke	10.000s	368.974us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	72.845us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	619.555us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	503.232us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	94.927us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	74.603us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	619.555us	20	20	100.00
		aes_csr_aliasing	3.000s	94.927us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	368.974us	50	50	100.00
		aes_config_error	27.000s	1.289ms	50	50	100.00
		aes_stress	17.000s	646.831us	50	50	100.00
V2	key_length	aes_smoke	10.000s	368.974us	50	50	100.00
		aes_config_error	27.000s	1.289ms	50	50	100.00
		aes_stress	17.000s	646.831us	50	50	100.00
V2	back2back	aes_stress	17.000s	646.831us	50	50	100.00
		aes_b2b	36.000s	530.318us	50	50	100.00
V2	backpressure	aes_stress	17.000s	646.831us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	368.974us	50	50	100.00
		aes_config_error	27.000s	1.289ms	50	50	100.00
		aes_stress	17.000s	646.831us	50	50	100.00
		aes_alert_reset	9.000s	158.234us	49	50	98.00
V2	failure_test	aes_man_cfg_err	5.000s	408.528us	50	50	100.00
		aes_config_error	27.000s	1.289ms	50	50	100.00
		aes_alert_reset	9.000s	158.234us	49	50	98.00
V2	trigger_clear_test	aes_clear	18.000s	1.373ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	428.440us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	158.234us	49	50	98.00
V2	stress	aes_stress	17.000s	646.831us	50	50	100.00
V2	sideload	aes_stress	17.000s	646.831us	50	50	100.00
		aes_sideload	23.000s	924.801us	50	50	100.00
V2	deinitialization	aes_deinit	26.000s	2.854ms	50	50	100.00
V2	stress_all	aes_stress_all	1.750m	4.184ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	159.541us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	200.731us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	200.731us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	72.845us	5	5	100.00
		aes_csr_rw	3.000s	619.555us	20	20	100.00
		aes_csr_aliasing	3.000s	94.927us	5	5	100.00
		aes_same_csr_outstanding	3.000s	109.436us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	72.845us	5	5	100.00
		aes_csr_rw	3.000s	619.555us	20	20	100.00
		aes_csr_aliasing	3.000s	94.927us	5	5	100.00
		aes_same_csr_outstanding	3.000s	109.436us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	26.000s	1.085ms	50	50	100.00
V2S	fault_inject	aes_fi	19.000s	4.106ms	50	50	100.00
		aes_control_fi	57.000s	10.018ms	281	300	93.67
		aes_cipher_fi	1.000m	10.026ms	343	350	98.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	443.545us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	443.545us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	443.545us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	443.545us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	265.039us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	808.123us	5	5	100.00
		aes_tl_intg_err	3.000s	330.454us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	330.454us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	158.234us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	443.545us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	368.974us	50	50	100.00
		aes_stress	17.000s	646.831us	50	50	100.00
		aes_alert_reset	9.000s	158.234us	49	50	98.00
		aes_core_fi	36.000s	10.007ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	443.545us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	124.851us	50	50	100.00
		aes_stress	17.000s	646.831us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	17.000s	646.831us	50	50	100.00
		aes_sideload	23.000s	924.801us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	124.851us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	124.851us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	124.851us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	124.851us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	124.851us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	17.000s	646.831us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	17.000s	646.831us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	19.000s	4.106ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	19.000s	4.106ms	50	50	100.00
		aes_control_fi	57.000s	10.018ms	281	300	93.67
		aes_cipher_fi	1.000m	10.026ms	343	350	98.00
		aes_ctr_fi	4.000s	188.839us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	19.000s	4.106ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	19.000s	4.106ms	50	50	100.00
		aes_control_fi	57.000s	10.018ms	281	300	93.67
		aes_cipher_fi	1.000m	10.026ms	343	350	98.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000m	10.026ms	343	350	98.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	19.000s	4.106ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	19.000s	4.106ms	50	50	100.00
		aes_control_fi	57.000s	10.018ms	281	300	93.67
		aes_ctr_fi	4.000s	188.839us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	19.000s	4.106ms	50	50	100.00
		aes_control_fi	57.000s	10.018ms	281	300	93.67
		aes_cipher_fi	1.000m	10.026ms	343	350	98.00
		aes_ctr_fi	4.000s	188.839us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	158.234us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	19.000s	4.106ms	50	50	100.00
		aes_control_fi	57.000s	10.018ms	281	300	93.67
		aes_cipher_fi	1.000m	10.026ms	343	350	98.00
		aes_ctr_fi	4.000s	188.839us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	19.000s	4.106ms	50	50	100.00
		aes_control_fi	57.000s	10.018ms	281	300	93.67
		aes_cipher_fi	1.000m	10.026ms	343	350	98.00
		aes_ctr_fi	4.000s	188.839us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	19.000s	4.106ms	50	50	100.00
		aes_control_fi	57.000s	10.018ms	281	300	93.67
		aes_ctr_fi	4.000s	188.839us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	19.000s	4.106ms	50	50	100.00
		aes_control_fi	57.000s	10.018ms	281	300	93.67
		aes_cipher_fi	1.000m	10.026ms	343	350	98.00
V2S		TOTAL			957	985	97.16
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	25.000s	740.900us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1563	1602	97.57

Failure Buckets

Job timed out after * minutes has 16 failures:
- Test aes_control_fi has 14 failures.
  - 10.aes_control_fi.97824888294493714616792518110665275627340063433116963715347520507684622976663
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_control_fi.86887842944263998592744834467436832311814453062658920919372281089512183734149
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 2 failures.
  - 62.aes_cipher_fi.47813807855391827064308143275611525256454943031685038350418656351505338162494
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/62.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 196.aes_cipher_fi.27961396958587108127614974905950340052705406780884081086074343601039100098798
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/196.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

2.aes_stress_all_with_rand_reset.76885740056328200262557120185870609042289998042662146377062496271681898495246
Line 454, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2199194263 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2199194263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.102824815393186687912024796855947186426932242767955118238563284778911160681500
Line 608, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 740900306 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 740900306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 1.aes_control_fi.82997210984872077010635739137489402592012684436164656107421121756167484834183
    Line 144, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008869087 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008869087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 97.aes_control_fi.17658105221268267966809786684683044038729752873967118153865606328727983066772
    Line 139, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/97.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006445399 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006445399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 61.aes_cipher_fi.51910489185006884452599208511234301510282838638128030319350652575965788668031
    Line 136, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/61.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10026271152 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026271152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 96.aes_cipher_fi.102452479627048915473484829648783156427078815855583194214392784236655701265116
    Line 147, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/96.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005151440 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005151440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.77569720408477106618485374625724361788312793523112177456387836819631327437320
    Line 259, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 923839892 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 923839892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.60458992987269683574782913907578160964708184461541053827918953395398685802296
    Line 362, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 603684782 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 603684782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 13.aes_core_fi.15343663325968105460154619768333732151679809833945496079573736368547669635904
    Line 146, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/13.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006760528 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006760528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 43.aes_core_fi.32407431639851449560836846319483355820757721033801037990909715234340821367841
    Line 146, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/43.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10058290360 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10058290360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.7947882226917455678382264855504253547105874047036064827112110812001833322879
    Line 166, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  61661866 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  61661866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.16857266922420149726504979615432164832636750147948935139183614480388732236325
    Line 170, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 112123009 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 112123009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 47.aes_alert_reset.99226695328835721703623687044707316033837221446939451873957470193864870295467
    Line 772, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/47.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 61251432 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 61168099 PS)
  UVM_ERROR @  61251432 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  61251432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```