AES/UNMASKED Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: `d00a6c8`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	70.700us	1	1	100.00
V1	smoke	aes_smoke	3.000s	62.070us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	79.528us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	65.831us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	591.019us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	107.258us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	59.820us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	65.831us	20	20	100.00
		aes_csr_aliasing	5.000s	107.258us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	3.000s	62.070us	50	50	100.00
		aes_config_error	4.000s	842.104us	50	50	100.00
		aes_stress	4.000s	72.105us	50	50	100.00
V2	key_length	aes_smoke	3.000s	62.070us	50	50	100.00
		aes_config_error	4.000s	842.104us	50	50	100.00
		aes_stress	4.000s	72.105us	50	50	100.00
V2	back2back	aes_stress	4.000s	72.105us	50	50	100.00
		aes_b2b	6.000s	385.585us	50	50	100.00
V2	backpressure	aes_stress	4.000s	72.105us	50	50	100.00
V2	multi_message	aes_smoke	3.000s	62.070us	50	50	100.00
		aes_config_error	4.000s	842.104us	50	50	100.00
		aes_stress	4.000s	72.105us	50	50	100.00
		aes_alert_reset	4.000s	245.327us	49	50	98.00
V2	failure_test	aes_man_cfg_err	3.000s	70.028us	50	50	100.00
		aes_config_error	4.000s	842.104us	50	50	100.00
		aes_alert_reset	4.000s	245.327us	49	50	98.00
V2	trigger_clear_test	aes_clear	4.000s	133.624us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	4.000s	213.970us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	245.327us	49	50	98.00
V2	stress	aes_stress	4.000s	72.105us	50	50	100.00
V2	sideload	aes_stress	4.000s	72.105us	50	50	100.00
		aes_sideload	3.000s	87.898us	50	50	100.00
V2	deinitialization	aes_deinit	4.000s	194.864us	50	50	100.00
V2	stress_all	aes_stress_all	22.000s	1.926ms	9	10	90.00
V2	alert_test	aes_alert_test	3.000s	53.149us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	78.025us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	78.025us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	79.528us	5	5	100.00
		aes_csr_rw	5.000s	65.831us	20	20	100.00
		aes_csr_aliasing	5.000s	107.258us	5	5	100.00
		aes_same_csr_outstanding	3.000s	91.761us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	79.528us	5	5	100.00
		aes_csr_rw	5.000s	65.831us	20	20	100.00
		aes_csr_aliasing	5.000s	107.258us	5	5	100.00
		aes_same_csr_outstanding	3.000s	91.761us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	4.000s	380.294us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	298.345us	49	50	98.00
		aes_control_fi	34.000s	10.022ms	278	300	92.67
		aes_cipher_fi	33.000s	10.003ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	91.817us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	91.817us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	91.817us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	91.817us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	639.753us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	1.479ms	5	5	100.00
		aes_tl_intg_err	10.000s	731.107us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	731.107us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	245.327us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	91.817us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	62.070us	50	50	100.00
		aes_stress	4.000s	72.105us	50	50	100.00
		aes_alert_reset	4.000s	245.327us	49	50	98.00
		aes_core_fi	17.000s	10.009ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	91.817us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	132.544us	50	50	100.00
		aes_stress	4.000s	72.105us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	72.105us	50	50	100.00
		aes_sideload	3.000s	87.898us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	132.544us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	132.544us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	132.544us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	132.544us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	132.544us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	72.105us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	72.105us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	298.345us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	298.345us	49	50	98.00
		aes_control_fi	34.000s	10.022ms	278	300	92.67
		aes_cipher_fi	33.000s	10.003ms	324	350	92.57
		aes_ctr_fi	3.000s	84.737us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	298.345us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	298.345us	49	50	98.00
		aes_control_fi	34.000s	10.022ms	278	300	92.67
		aes_cipher_fi	33.000s	10.003ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	33.000s	10.003ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	298.345us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	298.345us	49	50	98.00
		aes_control_fi	34.000s	10.022ms	278	300	92.67
		aes_ctr_fi	3.000s	84.737us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	298.345us	49	50	98.00
		aes_control_fi	34.000s	10.022ms	278	300	92.67
		aes_cipher_fi	33.000s	10.003ms	324	350	92.57
		aes_ctr_fi	3.000s	84.737us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	245.327us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	298.345us	49	50	98.00
		aes_control_fi	34.000s	10.022ms	278	300	92.67
		aes_cipher_fi	33.000s	10.003ms	324	350	92.57
		aes_ctr_fi	3.000s	84.737us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	298.345us	49	50	98.00
		aes_control_fi	34.000s	10.022ms	278	300	92.67
		aes_cipher_fi	33.000s	10.003ms	324	350	92.57
		aes_ctr_fi	3.000s	84.737us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	298.345us	49	50	98.00
		aes_control_fi	34.000s	10.022ms	278	300	92.67
		aes_ctr_fi	3.000s	84.737us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	298.345us	49	50	98.00
		aes_control_fi	34.000s	10.022ms	278	300	92.67
		aes_cipher_fi	33.000s	10.003ms	324	350	92.57
V2S		TOTAL			932	985	94.62
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	14.000s	772.240us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1537	1602	95.94

Failure Buckets

Job timed out after * minutes has 31 failures:
- Test aes_cipher_fi has 16 failures.
  - 17.aes_cipher_fi.32588066220085173447299921841019995263046015616681469239735124241208663828234
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 21.aes_cipher_fi.1005035541754304370015922697813106826572274352365674486793447350774870731653
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 14 more failures.
- Test aes_control_fi has 15 failures.
  - 24.aes_control_fi.10968798956856382091684315884116558687562576048082273574270336325995877399735
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 48.aes_control_fi.109140187822361040593542554261736621934539485434211234038762213422703311029073
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/48.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 2.aes_cipher_fi.75587597600186619512314444726533992752564098565056318995240444240050542996557
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10001934968 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001934968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 80.aes_cipher_fi.26760729687887433596652429930704683674909162588969527487742029367735327431548
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/80.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10017439813 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017439813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 36.aes_control_fi.43768409144727761000625551027000037504092416462703204703238660080589667922774
    Line 144, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002945027 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002945027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 111.aes_control_fi.57321832588530219194387496760443863053415752438088674498880801719598249244790
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/111.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10021908545 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021908545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.49405017813571395052800149601988322204911036760836117742507902202340196854133
Line 579, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 324031841 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 324031841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.76216653855153848347060412074617261835510348375547894832054805182351454422832
Line 360, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 772240436 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 772240436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_stress_all has 1 failures.

3.aes_stress_all.85897389694787550910577590776252404842282228980129933252728102111181835153065
Line 25472, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 118452263 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 118442263 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 118452263 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 118442263 PS)
  UVM_ERROR @ 118452263 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

Test aes_fi has 1 failures.

25.aes_fi.3265816149404842933238062266117322287926054686593218012344501967529901891926
Line 2471, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/25.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 8897425 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 8887008 PS)
  UVM_ERROR @   8897425 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   8897425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.36415119314258393669201517118855072414263997819630450616481778184133033492411
    Line 169, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  39823078 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  39823078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.aes_stress_all_with_rand_reset.74420072215728537080970630693614034046532909038505325832766440853413504168506
    Line 404, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 391680055 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 391680055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 6.aes_stress_all_with_rand_reset.93797522678640827760734720323271031439285603865586424074823363673628180459179
    Line 164, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  87190661 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  87190661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_stress_all_with_rand_reset.64868011400606897673935744531593186467222981661758636921533633529218807362845
    Line 151, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  94078231 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  94078231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 10.aes_core_fi.8414992762729787519178541659554876350791702288165965877529553128022811600656
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009154420 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009154420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 26.aes_core_fi.91685849550083204105519836094073009218950092640018420679085136865511939708424
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007295256 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007295256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 34.aes_core_fi.64863650128140751899048922259451144984790130915920359704944332852323221735446
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10044028689 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10044028689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 61.aes_core_fi.40849411983553850407726403600004053927772291260473506105955074578895588819325
    Line 134, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/61.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019276345 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019276345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 37.aes_alert_reset.12032858702486848171172846573340443294124330243004925525362949934081788109775
    Line 2790, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/37.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 42070481 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 42017849 PS)
  UVM_ERROR @  42070481 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  42070481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```