| V1 |
smoke |
aon_timer_smoke |
1.450s |
523.217us |
5 |
5 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
2.490s |
720.035us |
5 |
5 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
1.740s |
419.474us |
20 |
20 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
14.140s |
7.272ms |
5 |
5 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
1.900s |
506.735us |
5 |
5 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
1.500s |
544.606us |
20 |
20 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
1.740s |
419.474us |
20 |
20 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.900s |
506.735us |
5 |
5 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
2.000s |
369.737us |
5 |
5 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
1.570s |
475.688us |
5 |
5 |
100.00 |
| V1 |
|
TOTAL |
|
|
70 |
70 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
1.034m |
50.797ms |
15 |
15 |
100.00 |
| V2 |
jump |
aon_timer_jump |
2.060s |
660.987us |
5 |
5 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
3.236m |
134.752ms |
15 |
15 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
1.720s |
296.167us |
50 |
50 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
1.830s |
501.772us |
50 |
50 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
2.700s |
461.837us |
20 |
20 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
2.700s |
461.837us |
20 |
20 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
2.490s |
720.035us |
5 |
5 |
100.00 |
|
|
aon_timer_csr_rw |
1.740s |
419.474us |
20 |
20 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.900s |
506.735us |
5 |
5 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
6.180s |
2.188ms |
20 |
20 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
2.490s |
720.035us |
5 |
5 |
100.00 |
|
|
aon_timer_csr_rw |
1.740s |
419.474us |
20 |
20 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.900s |
506.735us |
5 |
5 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
6.180s |
2.188ms |
20 |
20 |
100.00 |
| V2 |
|
TOTAL |
|
|
175 |
175 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
12.580s |
8.694ms |
5 |
5 |
100.00 |
|
|
aon_timer_tl_intg_err |
12.130s |
8.547ms |
20 |
20 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
12.130s |
8.547ms |
20 |
20 |
100.00 |
| V2S |
|
TOTAL |
|
|
25 |
25 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
1.960s |
466.798us |
5 |
5 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
2.040s |
676.705us |
5 |
5 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
8.830s |
3.753ms |
5 |
5 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
2.410s |
621.986us |
10 |
10 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
8.040s |
4.264ms |
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
29.070s |
8.834ms |
15 |
15 |
100.00 |
| V3 |
|
TOTAL |
|
|
45 |
45 |
100.00 |
|
|
TOTAL |
|
|
315 |
315 |
100.00 |