CSRNG Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	37.000s	28.639us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	62.429us	5	5	100.00
V1	csr_rw	csrng_csr_rw	3.000s	13.480us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	34.000s	2.083ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	284.685us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	225.108us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	13.480us	20	20	100.00
		csrng_csr_aliasing	5.000s	284.685us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	39.000s	126.438us	200	200	100.00
V2	alerts	csrng_alert	46.000s	388.457us	500	500	100.00
V2	err	csrng_err	37.000s	19.636us	500	500	100.00
V2	cmds	csrng_cmds	8.767m	54.597ms	50	50	100.00
V2	life cycle	csrng_cmds	8.767m	54.597ms	50	50	100.00
V2	stress_all	csrng_stress_all	32.267m	165.569ms	49	50	98.00
V2	intr_test	csrng_intr_test	3.000s	88.557us	50	50	100.00
V2	alert_test	csrng_alert_test	37.000s	24.987us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	734.039us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	734.039us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	62.429us	5	5	100.00
		csrng_csr_rw	3.000s	13.480us	20	20	100.00
		csrng_csr_aliasing	5.000s	284.685us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	681.455us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	62.429us	5	5	100.00
		csrng_csr_rw	3.000s	13.480us	20	20	100.00
		csrng_csr_aliasing	5.000s	284.685us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	681.455us	20	20	100.00
V2		TOTAL			1439	1440	99.93
V2S	tl_intg_err	csrng_sec_cm	40.000s	296.680us	5	5	100.00
		csrng_tl_intg_err	8.000s	510.980us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	37.000s	19.106us	50	50	100.00
		csrng_csr_rw	3.000s	13.480us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	46.000s	388.457us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	32.267m	165.569ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
		csrng_sec_cm	40.000s	296.680us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
		csrng_sec_cm	40.000s	296.680us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
		csrng_sec_cm	40.000s	296.680us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
		csrng_sec_cm	40.000s	296.680us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
		csrng_sec_cm	40.000s	296.680us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
		csrng_sec_cm	40.000s	296.680us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
		csrng_sec_cm	40.000s	296.680us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	46.000s	388.457us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	32.267m	165.569ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	46.000s	388.457us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	8.000s	510.980us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
		csrng_sec_cm	40.000s	296.680us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
		csrng_sec_cm	40.000s	296.680us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	39.000s	126.438us	200	200	100.00
		csrng_err	37.000s	19.636us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	22.683m	100.329ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1629	1630	99.94

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
  • Test csrng_stress_all has 1 failures.

    • 5.csrng_stress_all.43726648338518297361086659067692637570366158439328712126875747955176624237245
      Line 155, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/5.csrng_stress_all/latest/run.log

        UVM_ERROR @ 4653018533 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 4653018533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---