DMA Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	9.000s	1.584ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	12.000s	1.687ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	9.000s	1.476ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	23.811us	5	5	100.00
V1	csr_rw	dma_csr_rw	2.000s	108.495us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	19.000s	29.731ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	447.178us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	74.208us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	108.495us	20	20	100.00
		dma_csr_aliasing	8.000s	447.178us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	2.417m	19.685ms	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	8.800m	156.222ms	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	9.200m	47.211ms	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	9.200m	47.211ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	8.800m	156.222ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	7.933m	86.535ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	9.200m	47.211ms	3	3	100.00
V2	dma_abort	dma_abort	24.000s	2.113ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	4.900m	33.264ms	3	3	100.00
V2	alert_test	dma_alert_test	2.000s	11.425us	50	50	100.00
V2	intr_test	dma_intr_test	2.000s	97.426us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	145.216us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	145.216us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	23.811us	5	5	100.00
		dma_csr_rw	2.000s	108.495us	20	20	100.00
		dma_csr_aliasing	8.000s	447.178us	5	5	100.00
		dma_same_csr_outstanding	3.000s	135.962us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	23.811us	5	5	100.00
		dma_csr_rw	2.000s	108.495us	20	20	100.00
		dma_csr_aliasing	8.000s	447.178us	5	5	100.00
		dma_same_csr_outstanding	3.000s	135.962us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	26.000s	383.457us	5	5	100.00
		dma_generic_stress	7.933m	86.535ms	5	5	100.00
		dma_handshake_stress	9.200m	47.211ms	3	3	100.00
V2S	dma_config_lock	dma_config_lock	13.000s	1.625ms	15	15	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	184.690us	20	20	100.00
		dma_sec_cm	2.000s	44.341us	5	5	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	3.117m	14.885ms	25	25	100.00
		dma_longer_transfer	8.000s	401.256us	5	5	100.00
		dma_stress_all_with_rand_reset	12.000s	1.476ms	0	1	0.00
		TOTAL			394	395	99.75

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.57693429887238423808255133376823745514869124298716591746908218188140151105948
      Line 100, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1476065252ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1476065252ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---