EDN Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.370s 16.765us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.920s 21.653us 5 5 100.00
V1 csr_rw edn_csr_rw 0.950s 18.382us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.670s 678.282us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.260s 44.655us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.480s 102.171us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.950s 18.382us 20 20 100.00
edn_csr_aliasing 1.260s 44.655us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.632m 9.129ms 300 300 100.00
V2 csrng_commands edn_genbits 1.632m 9.129ms 300 300 100.00
V2 genbits edn_genbits 1.632m 9.129ms 300 300 100.00
V2 interrupts edn_intr 1.500s 21.832us 50 50 100.00
V2 alerts edn_alert 1.710s 30.299us 200 200 100.00
V2 errs edn_err 1.600s 20.736us 100 100 100.00
V2 disable edn_disable 1.320s 13.564us 50 50 100.00
edn_disable_auto_req_mode 1.850s 49.141us 50 50 100.00
V2 stress_all edn_stress_all 5.500s 279.994us 50 50 100.00
V2 intr_test edn_intr_test 0.960s 31.369us 50 50 100.00
V2 alert_test edn_alert_test 1.530s 45.323us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.170s 1.776ms 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.170s 1.776ms 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.920s 21.653us 5 5 100.00
edn_csr_rw 0.950s 18.382us 20 20 100.00
edn_csr_aliasing 1.260s 44.655us 5 5 100.00
edn_same_csr_outstanding 1.200s 73.881us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.920s 21.653us 5 5 100.00
edn_csr_rw 0.950s 18.382us 20 20 100.00
edn_csr_aliasing 1.260s 44.655us 5 5 100.00
edn_same_csr_outstanding 1.200s 73.881us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.930s 688.517us 5 5 100.00
edn_tl_intg_err 4.560s 755.195us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.070s 46.954us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.710s 30.299us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.930s 688.517us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.930s 688.517us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.930s 688.517us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.930s 688.517us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.710s 30.299us 200 200 100.00
edn_sec_cm 7.930s 688.517us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.710s 30.299us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.560s 755.195us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.743m 22.485ms 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 1111 1130 98.32

Failure Buckets