HMAC Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 12.720s 4.621ms 10 10 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.200s 138.458us 5 5 100.00
V1 csr_rw hmac_csr_rw 1.300s 30.669us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 14.060s 11.301ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 8.920s 895.773us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 3.040s 32.014us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.300s 30.669us 20 20 100.00
hmac_csr_aliasing 8.920s 895.773us 5 5 100.00
V1 TOTAL 65 65 100.00
V2 long_msg hmac_long_msg 1.448m 1.795ms 10 10 100.00
V2 back_pressure hmac_back_pressure 1.516m 22.577ms 25 25 100.00
V2 test_vectors hmac_test_sha256_vectors 3.920m 24.486ms 30 30 100.00
hmac_test_sha384_vectors 9.551m 16.518ms 75 75 100.00
hmac_test_sha512_vectors 8.845m 13.345ms 75 75 100.00
hmac_test_hmac256_vectors 14.350s 1.381ms 50 50 100.00
hmac_test_hmac384_vectors 15.910s 350.517us 60 60 100.00
hmac_test_hmac512_vectors 20.220s 1.648ms 75 75 100.00
V2 burst_wr hmac_burst_wr 43.670s 4.020ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 18.558m 12.675ms 10 10 100.00
V2 error hmac_error 1.509m 7.939ms 10 10 100.00
V2 wipe_secret hmac_wipe_secret 2.108m 7.788ms 10 10 100.00
V2 save_and_restore hmac_smoke 12.720s 4.621ms 10 10 100.00
hmac_long_msg 1.448m 1.795ms 10 10 100.00
hmac_back_pressure 1.516m 22.577ms 25 25 100.00
hmac_datapath_stress 18.558m 12.675ms 10 10 100.00
hmac_burst_wr 43.670s 4.020ms 50 50 100.00
hmac_stress_all 26.083m 11.423ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 12.720s 4.621ms 10 10 100.00
hmac_long_msg 1.448m 1.795ms 10 10 100.00
hmac_back_pressure 1.516m 22.577ms 25 25 100.00
hmac_datapath_stress 18.558m 12.675ms 10 10 100.00
hmac_wipe_secret 2.108m 7.788ms 10 10 100.00
hmac_test_sha256_vectors 3.920m 24.486ms 30 30 100.00
hmac_test_sha384_vectors 9.551m 16.518ms 75 75 100.00
hmac_test_sha512_vectors 8.845m 13.345ms 75 75 100.00
hmac_test_hmac256_vectors 14.350s 1.381ms 50 50 100.00
hmac_test_hmac384_vectors 15.910s 350.517us 60 60 100.00
hmac_test_hmac512_vectors 20.220s 1.648ms 75 75 100.00
V2 wide_digest_configurable_key_length hmac_smoke 12.720s 4.621ms 10 10 100.00
hmac_long_msg 1.448m 1.795ms 10 10 100.00
hmac_back_pressure 1.516m 22.577ms 25 25 100.00
hmac_datapath_stress 18.558m 12.675ms 10 10 100.00
hmac_burst_wr 43.670s 4.020ms 50 50 100.00
hmac_error 1.509m 7.939ms 10 10 100.00
hmac_wipe_secret 2.108m 7.788ms 10 10 100.00
hmac_test_sha256_vectors 3.920m 24.486ms 30 30 100.00
hmac_test_sha384_vectors 9.551m 16.518ms 75 75 100.00
hmac_test_sha512_vectors 8.845m 13.345ms 75 75 100.00
hmac_test_hmac256_vectors 14.350s 1.381ms 50 50 100.00
hmac_test_hmac384_vectors 15.910s 350.517us 60 60 100.00
hmac_test_hmac512_vectors 20.220s 1.648ms 75 75 100.00
hmac_stress_all 26.083m 11.423ms 50 50 100.00
V2 stress_all hmac_stress_all 26.083m 11.423ms 50 50 100.00
V2 alert_test hmac_alert_test 0.930s 15.109us 50 50 100.00
V2 intr_test hmac_intr_test 0.980s 41.256us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.580s 834.264us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.580s 834.264us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.200s 138.458us 5 5 100.00
hmac_csr_rw 1.300s 30.669us 20 20 100.00
hmac_csr_aliasing 8.920s 895.773us 5 5 100.00
hmac_same_csr_outstanding 2.990s 159.857us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.200s 138.458us 5 5 100.00
hmac_csr_rw 1.300s 30.669us 20 20 100.00
hmac_csr_aliasing 8.920s 895.773us 5 5 100.00
hmac_same_csr_outstanding 2.990s 159.857us 20 20 100.00
V2 TOTAL 670 670 100.00
V2S tl_intg_err hmac_sec_cm 1.140s 67.214us 5 5 100.00
hmac_tl_intg_err 4.820s 863.013us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.820s 863.013us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 12.720s 4.621ms 10 10 100.00
V3 stress_reset hmac_stress_reset 6.870s 615.782us 25 25 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 11.299m 183.688ms 35 35 100.00
V3 TOTAL 60 60 100.00
Unmapped tests hmac_directed 1.260s 37.460us 1 1 100.00
TOTAL 821 821 100.00