I2C Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: `d00a6c8`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.329m	2.003ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	31.360s	999.858us	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.120s	19.771us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.120s	20.322us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.610s	548.993us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.070s	40.367us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.680s	58.714us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.120s	20.322us	20	20	100.00
		i2c_csr_aliasing	2.070s	40.367us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	5.090s	970.934us	2	50	4.00
V2	host_stress_all	i2c_host_stress_all	28.963m	19.809ms	6	50	12.00
V2	host_maxperf	i2c_host_perf	49.587m	52.554ms	50	50	100.00
V2	host_override	i2c_host_override	1.060s	98.193us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.070m	19.779ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.422m	4.836ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.830s	742.408us	50	50	100.00
		i2c_host_fifo_fmt_empty	23.470s	557.902us	50	50	100.00
		i2c_host_fifo_reset_rx	11.550s	2.962ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.331m	3.341ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	39.200s	941.863us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	7.330s	761.827us	9	50	18.00
V2	target_glitch	i2c_target_glitch	2.840s	2.262ms	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	37.283m	75.555ms	49	50	98.00
V2	target_maxperf	i2c_target_perf	7.730s	865.265us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.040m	6.852ms	50	50	100.00
		i2c_target_intr_smoke	9.800s	2.640ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.330s	1.112ms	50	50	100.00
		i2c_target_fifo_reset_tx	2.570s	1.050ms	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	26.662m	68.055ms	50	50	100.00
		i2c_target_stress_rd	1.040m	6.852ms	50	50	100.00
		i2c_target_intr_stress_wr	6.421m	51.359ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	10.000s	5.756ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	59.830s	4.547ms	41	50	82.00
V2	bad_address	i2c_target_bad_addr	8.720s	1.544ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	36.310s	10.168ms	25	50	50.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.200s	569.467us	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.260s	228.083us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	49.587m	52.554ms	50	50	100.00
		i2c_host_perf_precise	2.694m	24.746ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	39.200s	941.863us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	26.340s	2.262ms	46	50	92.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.150s	1.721ms	50	50	100.00
		i2c_target_nack_acqfull_addr	4.370s	3.079ms	50	50	100.00
		i2c_target_nack_txstretch	2.280s	168.157us	32	50	64.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	25.580s	662.186us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.480s	3.734ms	50	50	100.00
V2	alert_test	i2c_alert_test	1.000s	173.630us	50	50	100.00
V2	intr_test	i2c_intr_test	1.050s	19.852us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.360s	254.832us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.360s	254.832us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.120s	19.771us	5	5	100.00
		i2c_csr_rw	1.120s	20.322us	20	20	100.00
		i2c_csr_aliasing	2.070s	40.367us	5	5	100.00
		i2c_same_csr_outstanding	1.450s	27.974us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.120s	19.771us	5	5	100.00
		i2c_csr_rw	1.120s	20.322us	20	20	100.00
		i2c_csr_aliasing	2.070s	40.367us	5	5	100.00
		i2c_same_csr_outstanding	1.450s	27.974us	20	20	100.00
V2		TOTAL			1599	1792	89.23
V2S	tl_intg_err	i2c_tl_intg_err	2.760s	366.264us	20	20	100.00
		i2c_sec_cm	1.460s	71.448us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.760s	366.264us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	41.180s	5.242ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.870s	402.583us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	17.460s	11.612ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1779	2042	87.12

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 95 failures:

Test i2c_host_error_intr has 48 failures.

0.i2c_host_error_intr.10413333147041052309432677818154780463235340446365926524540286199743716710570
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @   8297572 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @   8297572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.75695435355675561914062483845673780220384699119938304214518816216240953387365
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  95127643 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  95127643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 46 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

0.i2c_target_stress_all_with_rand_reset.85050476054560913424863259131666913446457365226651139949340132829996471469778
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 406447632 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 406447632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all_with_rand_reset.115709669616357805002480263992326281444218748499376759745034827980259099323423
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  48747279 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  48747279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test i2c_host_stress_all has 29 failures.

3.i2c_host_stress_all.27179581282012486243266105550150836515749618042424714235610292055783330619679
Line 95, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @  31122319 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  31122319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_host_stress_all.42110369586246120148353154300563611635293011488407658666712850246254981957759
Line 205, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 27919795832 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 27919795832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 27 more failures.

Test i2c_host_mode_toggle has 14 failures.

7.i2c_host_mode_toggle.35999619673999194730035225123151380605907263479360416536906601480053578628130
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 113268847 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 113268847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.i2c_host_mode_toggle.26269819873869295997932623079769610133306411097756583907501136367217706487879
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 261994916 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 261994916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 25 failures:
- Test i2c_target_hrst has 25 failures.
  - 0.i2c_target_hrst.96856480994053010988037981630352899423914402032029734023539231509668965308934
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10277833140 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10277833140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.35869288183141914126619111306888458535719417633472104442144114563553232065758
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10157879667 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10157879667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 23 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 22 failures:
- Test i2c_target_unexp_stop has 22 failures.
  - 0.i2c_target_unexp_stop.29660761316808684952070947688954071621716081533205537399753244457180054054704
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1223318611 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1223318611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.89172237969751190647194690835366243760095546450569641249382260137397047246287
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1126036390 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1126036390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 22 failures:
- Test i2c_target_unexp_stop has 22 failures.
  - 1.i2c_target_unexp_stop.63644473928134346997713815567896246864003122535770474498598223951576785669457
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 100669110 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 145 [0x91])
  UVM_INFO @ 100669110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.104545855882454504585855498793941958319171242552648663300152377080126868618511
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  67735652 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 66 [0x42])
  UVM_INFO @  67735652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 18 failures:
- Test i2c_target_nack_txstretch has 18 failures.
  - 0.i2c_target_nack_txstretch.80039129754091674035769073475002373324768893799871927453079475209794665821983
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 198075497 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 198075497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_nack_txstretch.44924412875592004426765230436317629064525853485675012692648404475540100469621
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 143121282 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 143121282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 16 failures:

Test i2c_host_mode_toggle has 16 failures.

3.i2c_host_mode_toggle.111176859196833819405056293745462499194336392839392473675117780187399977958095
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 235798372 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

4.i2c_host_mode_toggle.96461641887587613072603314043154924108814032222914075697728542589877574301818
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  31628362 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 14 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.39754992235293440765437943501295630043775124683607396606376808919885012224960
Line 105, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1751202831 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1751202831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.23098470698755652784020003096293754980064356399004991005993749244392185419962
Line 104, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 503752865 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 503752865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

2.i2c_target_stress_all_with_rand_reset.94792444577094340905628320621898454580812984618293696186574090647101673099727
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 412887119 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 412887119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_target_stress_all_with_rand_reset.82383422790468891328574786719028732966459678133570762898274461566284873651929
Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 955967018 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 955967018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 13 failures:

Test i2c_host_stress_all has 6 failures.

0.i2c_host_stress_all.86758644962605183220236329880977320081404008751779100644723980382576065773185
Line 128, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 26000625337 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4260215

1.i2c_host_stress_all.24271266297643382327910774488882032878575000332610674376876069214988164999565
Line 136, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 77140072039 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @9223847

... and 4 more failures.

Test i2c_host_mode_toggle has 7 failures.

14.i2c_host_mode_toggle.51293287715618954789546427223154965645213544758593517844991636105894485192131
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 127605976 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @36646

25.i2c_host_mode_toggle.47572856324785414243826049872513356814806432067070456943735682129636719302762
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/25.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 101105085 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @17862

... and 5 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 9 failures:
- Test i2c_target_stretch has 9 failures.
  - 2.i2c_target_stretch.64040957277943248221134454388933211943363680488425178628313205462286106823725
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10014224316 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10014224316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_stretch.1023844161553720585099088877283263169334367295799610942759527327874810708471
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10001429227 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10001429227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
Job timed out after * minutes has 8 failures:
- Test i2c_host_stress_all has 8 failures.
  - 8.i2c_host_stress_all.1732633687044074548947481703204196517684179384540018615329075839703520866972
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 11.i2c_host_stress_all.71238021843675092590224279625858813862388016604452650311575870483792167959810
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 6 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:

Test i2c_target_unexp_stop has 6 failures.

16.i2c_target_unexp_stop.74836159260147282397151623820068943676437586072021792954737490085396107676910
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 364195543 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 364195543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.i2c_target_unexp_stop.90995144187426157545189027221494673455901492678647176459186647312091476769380
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/30.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 251825798 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 251825798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
- Test i2c_host_mode_toggle has 4 failures.
  - 1.i2c_host_mode_toggle.105027147419590337097496673247098198080983317104929524715669421983847098308028
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  70817049 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x5c0cc94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  70817049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_host_mode_toggle.31284737579739650333496781499397205539519306201760397067422245642945386102811
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 119620884 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xc8838214, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 119620884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test i2c_target_tx_stretch_ctrl has 4 failures.
  - 1.i2c_target_tx_stretch_ctrl.39141215747398472006983088771653630203326728580149318476105256081122463227220
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 17.i2c_target_tx_stretch_ctrl.62720778302111741677717093586923083967696923650921869105929372164672954199746
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 2 more failures.

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.67711327098396593436571985833561318310156991688873971328930370888696248840023
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 2261625052 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 2261625052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.26376095137394938506885146035278540517068294862422053251070554763545064433908
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 2197770796 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 2197770796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 1.i2c_target_stress_all_with_rand_reset.51753115081913651400666561882109572234816828580128372818775811741270744690447
    Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 591080083 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 591080083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_stress_all_with_rand_reset.68371805307645502827898999602109443471014504314814731396251269774407185589450
    Line 100, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2903254642 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2903254642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
- Test i2c_target_intr_stress_wr has 1 failures.
  - 3.i2c_target_intr_stress_wr.20250346772747146360464419026506452192286927430403944307265892762917217488063
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 51358772791 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 51358772791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all has 1 failures.
  - 11.i2c_target_stress_all.106046601930744035141613602298000402880448108291510927705868891642447523844578
    Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 27225775456 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 27225775456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 2.i2c_host_stress_all.76266348500545027995601140749157228582500635397815458020497507026511082361632
    Line 126, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 36658067046 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```