KEYMGR Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	29.730s	5.272ms	50	50	100.00
V1	random	keymgr_random	43.130s	16.603ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.630s	65.353us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.860s	32.864us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	25.100s	7.117ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	16.040s	3.546ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.580s	49.539us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.860s	32.864us	20	20	100.00
		keymgr_csr_aliasing	16.040s	3.546ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.565m	2.517ms	49	50	98.00
V2	sideload	keymgr_sideload	35.810s	2.832ms	50	50	100.00
		keymgr_sideload_kmac	38.810s	7.577ms	50	50	100.00
		keymgr_sideload_aes	29.980s	1.708ms	50	50	100.00
		keymgr_sideload_otbn	36.330s	1.534ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	32.730s	5.725ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	6.160s	943.004us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	12.730s	2.500ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	57.390s	8.392ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	33.510s	3.213ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	14.030s	1.928ms	50	50	100.00
V2	stress_all	keymgr_stress_all	5.123m	19.731ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.180s	25.276us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.320s	14.699us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.250s	322.505us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.250s	322.505us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.630s	65.353us	5	5	100.00
		keymgr_csr_rw	1.860s	32.864us	20	20	100.00
		keymgr_csr_aliasing	16.040s	3.546ms	5	5	100.00
		keymgr_same_csr_outstanding	3.080s	434.973us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.630s	65.353us	5	5	100.00
		keymgr_csr_rw	1.860s	32.864us	20	20	100.00
		keymgr_csr_aliasing	16.040s	3.546ms	5	5	100.00
		keymgr_same_csr_outstanding	3.080s	434.973us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
		keymgr_tl_intg_err	8.420s	513.243us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.740s	418.243us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.740s	418.243us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.740s	418.243us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.740s	418.243us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.820s	2.188ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.420s	513.243us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.740s	418.243us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.565m	2.517ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	43.130s	16.603ms	50	50	100.00
		keymgr_csr_rw	1.860s	32.864us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	43.130s	16.603ms	50	50	100.00
		keymgr_csr_rw	1.860s	32.864us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	43.130s	16.603ms	50	50	100.00
		keymgr_csr_rw	1.860s	32.864us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	6.160s	943.004us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	33.510s	3.213ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	33.510s	3.213ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	43.130s	16.603ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	14.500s	1.053ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	7.110s	572.613us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	6.160s	943.004us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	7.110s	572.613us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	7.110s	572.613us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	7.110s	572.613us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	19.230s	1.244ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	7.110s	572.613us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	21.270s	3.577ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1088	1110	98.02

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test keymgr_stress_all_with_rand_reset has 18 failures.

    • 6.keymgr_stress_all_with_rand_reset.98303618586898554093592222514846470549534581995651145635477883074371652958673
      Line 769, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1485678419 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1485678419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.keymgr_stress_all_with_rand_reset.111612072475574845564707476449975389396143811328221203950997068672522928410209
      Line 522, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1003216193 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1003216193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_stress_all has 1 failures.

    • 24.keymgr_stress_all.280128118646345490070057137709231076858973140927400930466966937489073246747
      Line 196, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/24.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 838172337 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 838172337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_cfg_regwen has 1 failures.

    • 45.keymgr_cfg_regwen.103736424113585436960801182987163325134575477652632859031504335649679394359441
      Line 460, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @ 301700547 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 301700547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:

  • Test keymgr_lc_disable has 1 failures.

    • 27.keymgr_lc_disable.59987929134357706869319864705840379171392236769238364416959732471728674442100
      Line 426, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/27.keymgr_lc_disable/latest/run.log

        UVM_ERROR @ 357024091 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_0
        UVM_INFO @ 357024091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 35.keymgr_stress_all.46049200495526027102326770095106073081667093596520424288709753367345749191600
      Line 1025, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 265821283 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_6
        UVM_INFO @ 265821283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---