KEYMGR_DPE Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	6.313m	65.002ms	50	50	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.250s	27.838us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.210s	48.362us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	11.220s	1.181ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	6.350s	475.174us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.780s	528.661us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.210s	48.362us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.350s	475.174us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	intr_test	keymgr_dpe_intr_test	1.060s	49.486us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.240s	16.125us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.750s	532.556us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.750s	532.556us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.250s	27.838us	5	5	100.00
		keymgr_dpe_csr_rw	1.210s	48.362us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.350s	475.174us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.250s	65.649us	19	20	95.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.250s	27.838us	5	5	100.00
		keymgr_dpe_csr_rw	1.210s	48.362us	20	20	100.00
		keymgr_dpe_csr_aliasing	6.350s	475.174us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.250s	65.649us	19	20	95.00
V2		TOTAL			139	140	99.29
V2S	tl_intg_err	keymgr_dpe_sec_cm	15.690s	697.839us	5	5	100.00
		keymgr_dpe_tl_intg_err	6.360s	3.416ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.790s	234.939us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.790s	234.939us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.790s	234.939us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.790s	234.939us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	6.410s	1.103ms	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	15.690s	697.839us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	15.690s	697.839us	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			309	310	99.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:642) [keymgr_dpe_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
  • Test keymgr_dpe_same_csr_outstanding has 1 failures.

    • 1.keymgr_dpe_same_csr_outstanding.69455742748425074492163424194747454058281442417733933279576338585358300160907
      Line 77, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/1.keymgr_dpe_same_csr_outstanding/latest/run.log

        UVM_ERROR @   1113708 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed masked_data == exp_data (256 [0x100] vs 0 [0x0]) addr 0xbc5af5d0 read out mismatch
        UVM_INFO @   1113708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---