KMAC/MASKED Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.265m	11.671ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.300s	34.562us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.280s	31.774us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.220s	1.325ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.760s	144.618us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.860s	136.932us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.280s	31.774us	20	20	100.00
		kmac_csr_aliasing	6.760s	144.618us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.110s	39.814us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	27.810us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.139h	560.911ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.979m	52.380ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.755m	164.786ms	5	5	100.00
		kmac_test_vectors_sha3_256	37.225m	220.775ms	5	5	100.00
		kmac_test_vectors_sha3_384	29.009m	67.651ms	4	5	80.00
		kmac_test_vectors_sha3_512	19.695m	32.864ms	5	5	100.00
		kmac_test_vectors_shake_128	46.782m	455.879ms	5	5	100.00
		kmac_test_vectors_shake_256	25.065m	69.832ms	5	5	100.00
		kmac_test_vectors_kmac	3.460s	79.460us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.610s	111.381us	5	5	100.00
V2	sideload	kmac_sideload	9.321m	104.146ms	50	50	100.00
V2	app	kmac_app	6.386m	66.259ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.481m	55.785ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.405m	37.052ms	50	50	100.00
V2	error	kmac_error	7.508m	32.411ms	49	50	98.00
V2	key_error	kmac_key_error	17.530s	9.354ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	10.890s	1.279ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.300s	1.443ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.810s	23.226ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.144m	32.042ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.370s	2.950ms	50	50	100.00
V2	stress_all	kmac_stress_all	50.056m	128.398ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.030s	49.937us	50	50	100.00
V2	alert_test	kmac_alert_test	1.280s	103.870us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.940s	2.538ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.940s	2.538ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.300s	34.562us	5	5	100.00
		kmac_csr_rw	1.280s	31.774us	20	20	100.00
		kmac_csr_aliasing	6.760s	144.618us	5	5	100.00
		kmac_same_csr_outstanding	2.540s	159.407us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.300s	34.562us	5	5	100.00
		kmac_csr_rw	1.280s	31.774us	20	20	100.00
		kmac_csr_aliasing	6.760s	144.618us	5	5	100.00
		kmac_same_csr_outstanding	2.540s	159.407us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.490s	456.708us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.490s	456.708us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.490s	456.708us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.490s	456.708us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.030s	488.042us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.685m	30.494ms	5	5	100.00
		kmac_tl_intg_err	3.980s	1.327ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.980s	1.327ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.370s	2.950ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.265m	11.671ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.321m	104.146ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.490s	456.708us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.685m	30.494ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.685m	30.494ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.685m	30.494ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.265m	11.671ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.370s	2.950ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.685m	30.494ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.074m	15.994ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.265m	11.671ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	6.815m	7.227ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			933	940	99.26

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 4.kmac_stress_all_with_rand_reset.70915810875499826790102840730885189861598064097203800933425190883211698001832
      Line 521, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7226637572 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 7226637572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.kmac_stress_all_with_rand_reset.28361332866402064056682558876855178196828981189282240833289544240700511623775
      Line 216, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3506011187 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 3506011187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test kmac_burst_write has 1 failures.

    • 13.kmac_burst_write.63119160666723508114287976182849697309855680806312246712335204587085897258169
      Line 247, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_burst_write/latest/run.log

        UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_error has 1 failures.

    • 49.kmac_error.67930862664854375641359106741859277926402176704844470666458462732441948608862
      Line 217, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/49.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_test_vectors_sha3_384 has 1 failures.

    • 2.kmac_test_vectors_sha3_384.70204207196693445555774593982621606073252846353832163286622313076716912993139
      Line 75, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest/run.log

        UVM_ERROR @  48237633 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  48237633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 2.kmac_stress_all_with_rand_reset.24018339081284645227242514421524374106552942597418324397833801156904296496188
      Line 117, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1656440868 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1656440868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 6.kmac_shadow_reg_errors_with_csr_rw.17837479418383207708862478191627723863500286168021511340046781685882133575264
      Line 168, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  18010236 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (4254715624 [0xfd99cee8] vs 0 [0x0]) Regname: kmac_reg_block.prefix_1 reset value: 0x0
        UVM_INFO @  18010236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---