MBX Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.017m	7.748ms	2	2	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.000s	47.073us	5	5	100.00
V1	csr_rw	mbx_csr_rw	2.000s	14.416us	20	20	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	5.000s	1.201ms	5	5	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.000s	71.055us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	3.000s	58.849us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	14.416us	20	20	100.00
		mbx_csr_aliasing	2.000s	71.055us	5	5	100.00
V1		TOTAL			57	57	100.00
V2	mbx_stress	mbx_stress	2.233m	11.661ms	1	2	50.00
V2	mbx_max_activity	mbx_stress_zero_delays	1.867m	16.083ms	1	2	50.00
V2	mbx_imbx_oob	mbx_imbx_oob	42.000s	4.648ms	1	2	50.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	25.000s	4.870ms	5	5	100.00
V2	alert_test	mbx_alert_test	3.000s	135.658us	50	50	100.00
V2	intr_test	mbx_intr_test	2.000s	43.199us	50	50	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	5.000s	426.786us	20	20	100.00
V2	tl_d_illegal_access	mbx_tl_errors	5.000s	426.786us	20	20	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.000s	47.073us	5	5	100.00
		mbx_csr_rw	2.000s	14.416us	20	20	100.00
		mbx_csr_aliasing	2.000s	71.055us	5	5	100.00
		mbx_same_csr_outstanding	2.000s	110.043us	20	20	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.000s	47.073us	5	5	100.00
		mbx_csr_rw	2.000s	14.416us	20	20	100.00
		mbx_csr_aliasing	2.000s	71.055us	5	5	100.00
		mbx_same_csr_outstanding	2.000s	110.043us	20	20	100.00
V2		TOTAL			148	151	98.01
V2S	tl_intg_err	mbx_tl_intg_err	4.000s	184.426us	20	20	100.00
		mbx_sec_cm	2.000s	39.211us	5	5	100.00
V2S		TOTAL			25	25	100.00
		TOTAL			230	233	98.71

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 3 failures:

  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.104835535252182157068504819819185257575526817635206029706473717313833653028067
      Line 229, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @ 127806351 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 127806351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_stress has 1 failures.

    • 1.mbx_stress.100440046454214178952575707473006752681317553675496176935242222679653107174434
      Line 959, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress/latest/run.log

        UVM_ERROR @ 3199697699 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 3199697699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_imbx_oob has 1 failures.

    • 1.mbx_imbx_oob.109952467665287777649495184471298187765306304236615803747611944052317999855261
      Line 124, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_imbx_oob/latest/run.log

        UVM_ERROR @ 2510632233 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 2510632233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---