OTBN Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 12.000s 150.825us 0 1 0.00
V1 single_binary otbn_single 40.000s 487.244us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 21.530us 5 5 100.00
V1 csr_rw otbn_csr_rw 8.000s 26.777us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 8.000s 100.389us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 43.798us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 9.000s 137.223us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 8.000s 26.777us 20 20 100.00
otbn_csr_aliasing 4.000s 43.798us 5 5 100.00
V1 mem_walk otbn_mem_walk 52.000s 19.721ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 23.000s 397.146us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 51.000s 211.152us 0 10 0.00
V2 multi_error otbn_multi_err 49.000s 774.394us 0 1 0.00
V2 back_to_back otbn_multi 1.767m 385.540us 0 10 0.00
V2 stress_all otbn_stress_all 3.933m 1.168ms 0 10 0.00
V2 lc_escalation otbn_escalate 19.000s 65.658us 18 60 30.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 8.000s 18.239us 4 5 80.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 20.000s 92.576us 0 10 0.00
V2 alert_test otbn_alert_test 7.000s 23.155us 50 50 100.00
V2 intr_test otbn_intr_test 7.000s 30.091us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 8.000s 197.156us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 8.000s 197.156us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 21.530us 5 5 100.00
otbn_csr_rw 8.000s 26.777us 20 20 100.00
otbn_csr_aliasing 4.000s 43.798us 5 5 100.00
otbn_same_csr_outstanding 6.000s 24.248us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 21.530us 5 5 100.00
otbn_csr_rw 8.000s 26.777us 20 20 100.00
otbn_csr_aliasing 4.000s 43.798us 5 5 100.00
otbn_same_csr_outstanding 6.000s 24.248us 20 20 100.00
V2 TOTAL 162 246 65.85
V2S mem_integrity otbn_imem_err 16.545s 0 10 0.00
otbn_dmem_err 19.000s 64.041us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 12.000s 26.745us 0 5 0.00
otbn_controller_ispr_rdata_err 46.000s 161.708us 0 5 0.00
otbn_mac_bignum_acc_err 25.000s 87.665us 0 5 0.00
otbn_urnd_err 10.000s 24.701us 0 2 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 10.000s 38.286us 4 5 80.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 8.000s 34.131us 1 2 50.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 6.000s 7.662us 7 10 70.00
V2S tl_intg_err otbn_sec_cm 4.283m 5.804ms 3 5 60.00
otbn_tl_intg_err 52.000s 308.557us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 31.000s 408.863us 17 20 85.00
V2S prim_fsm_check otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 12.000s 150.825us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 19.000s 64.041us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 16.545s 0 10 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 52.000s 308.557us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 19.000s 65.658us 18 60 30.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 16.545s 0 10 0.00
otbn_dmem_err 19.000s 64.041us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 18.239us 4 5 80.00
otbn_illegal_mem_acc 10.000s 38.286us 4 5 80.00
otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 40.000s 487.244us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 16.545s 0 10 0.00
otbn_dmem_err 19.000s 64.041us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 18.239us 4 5 80.00
otbn_illegal_mem_acc 10.000s 38.286us 4 5 80.00
otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 19.000s 65.658us 18 60 30.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 16.545s 0 10 0.00
otbn_dmem_err 19.000s 64.041us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 18.239us 4 5 80.00
otbn_illegal_mem_acc 10.000s 38.286us 4 5 80.00
otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 40.000s 487.244us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 11.000s 38.226us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 10.000s 23.376us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 54.000s 1.376ms 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 54.000s 1.376ms 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 11.000s 48.857us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 16.000s 369.576us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 10.000s 58.352us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 10.000s 58.352us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 12.000s 63.422us 3 7 42.86
V2S sec_cm_data_mem_sec_wipe otbn_single 40.000s 487.244us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 40.000s 487.244us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 40.000s 487.244us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 1.767m 385.540us 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 40.000s 487.244us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 40.000s 487.244us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 18.000s 115.634us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 40.000s 487.244us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.283m 5.804ms 3 5 60.00
V2S TOTAL 60 163 36.81
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 10.100m 7.901ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 287 585 49.06

Failure Buckets