ROM_CTRL/32KB Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.490s	140.392us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.780s	307.159us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.760s	167.570us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.660s	174.053us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.690s	171.939us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.610s	2.041ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.760s	167.570us	20	20	100.00
		rom_ctrl_csr_aliasing	6.690s	171.939us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.890s	288.311us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.290s	8.206ms	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.000s	526.939us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	27.090s	8.304ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.520s	312.228us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	6.480s	166.016us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.850s	188.451us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.850s	188.451us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.780s	307.159us	5	5	100.00
		rom_ctrl_csr_rw	6.760s	167.570us	20	20	100.00
		rom_ctrl_csr_aliasing	6.690s	171.939us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.150s	300.496us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.780s	307.159us	5	5	100.00
		rom_ctrl_csr_rw	6.760s	167.570us	20	20	100.00
		rom_ctrl_csr_aliasing	6.690s	171.939us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.150s	300.496us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.740m	2.981ms	17	20	85.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	25.330s	3.170ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.125m	1.657ms	2	5	40.00
		rom_ctrl_tl_intg_err	1.025m	997.957us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.125m	1.657ms	2	5	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.125m	1.657ms	2	5	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.740m	2.981ms	17	20	85.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.740m	2.981ms	17	20	85.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.740m	2.981ms	17	20	85.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.740m	2.981ms	17	20	85.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.740m	2.981ms	17	20	85.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.125m	1.657ms	2	5	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.125m	1.657ms	2	5	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.490s	140.392us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.490s	140.392us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.490s	140.392us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.025m	997.957us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.740m	2.981ms	17	20	85.00
		rom_ctrl_kmac_err_chk	9.520s	312.228us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.740m	2.981ms	17	20	85.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.740m	2.981ms	17	20	85.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.740m	2.981ms	17	20	85.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	25.330s	3.170ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.125m	1.657ms	2	5	40.00
V2S		TOTAL			59	65	90.77
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.730m	14.275ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			260	266	97.74

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.

    • 5.rom_ctrl_corrupt_sig_fatal_chk.97323985959034989819760027463840045052971709662645817874674798370592279185954
      Line 87, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 647027517 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 647027517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.rom_ctrl_corrupt_sig_fatal_chk.69306700472971027156465387800868815603932094363724822167139744781601634222416
      Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1022525861 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1022525861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 0.rom_ctrl_sec_cm.103100461160405192820566701030907990101552056155004849701491998621311782805078
      Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 2182714ps failed at 2182714ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 2182714ps failed at 2182714ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

    • 1.rom_ctrl_sec_cm.31485498707000140278267848439275163757322217276417747164103468616876679770248
      Line 108, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 4029365ps failed at 4029365ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 6276622ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 6276622ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
      

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 3.rom_ctrl_sec_cm.52260494259391556518671996703281924241456795543799254109912853809077310148884
      Line 247, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 58737072ps failed at 58737072ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 58775534ps failed at 58775534ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'