ROM_CTRL/64KB Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	12.820s	4.164ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	19.180s	568.096us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.160s	2.566ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.760s	290.187us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.200s	214.359us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	12.620s	4.365ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.160s	2.566ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.200s	214.359us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.940s	2.068ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.300s	4.961ms	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.770s	663.752us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	52.020s	7.972ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	17.300s	3.133ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	14.970s	2.138ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.000s	1.137ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.000s	1.137ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	19.180s	568.096us	5	5	100.00
		rom_ctrl_csr_rw	15.160s	2.566ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.200s	214.359us	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.020s	311.311us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	19.180s	568.096us	5	5	100.00
		rom_ctrl_csr_rw	15.160s	2.566ms	20	20	100.00
		rom_ctrl_csr_aliasing	10.200s	214.359us	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.020s	311.311us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	5.454m	111.995ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.257m	33.105ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	10.248m	734.931us	1	5	20.00
		rom_ctrl_tl_intg_err	2.086m	1.203ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	10.248m	734.931us	1	5	20.00
V2S	prim_count_check	rom_ctrl_sec_cm	10.248m	734.931us	1	5	20.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.454m	111.995ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.454m	111.995ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	5.454m	111.995ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.454m	111.995ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.454m	111.995ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	10.248m	734.931us	1	5	20.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	10.248m	734.931us	1	5	20.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	12.820s	4.164ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	12.820s	4.164ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	12.820s	4.164ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.086m	1.203ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	5.454m	111.995ms	20	20	100.00
		rom_ctrl_kmac_err_chk	17.300s	3.133ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	5.454m	111.995ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	5.454m	111.995ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	5.454m	111.995ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.257m	33.105ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	10.248m	734.931us	1	5	20.00
V2S		TOTAL			61	65	93.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.190m	4.482ms	19	20	95.00
V3		TOTAL			19	20	95.00
		TOTAL			261	266	98.12

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 0.rom_ctrl_sec_cm.108409738377445257148143319049323859041131099293036180050517036220395942812051
      Line 289, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 71644970ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 71644970ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 71644970ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

    • 2.rom_ctrl_sec_cm.47370587375568802041377563958798614571791544856048974686610974452669510926739
      Line 304, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 28357726ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 28357726ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 28357726ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 1.rom_ctrl_sec_cm.85569665565151584587791967857962190776715727741200220294296217873390057705705
      Line 175, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 9971571ps failed at 9971571ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 9971571ps failed at 9971571ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 3.rom_ctrl_sec_cm.83881079880185422102276078037357166444429695894344268766005665025509834940569
      Line 162, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 4217794ps failed at 4217794ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 4227895ps failed at 4227895ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

• UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire has 1 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 8.rom_ctrl_stress_all_with_rand_reset.737208012451106847252156549128888914011879171068883992432999699684837490892
      Line 150, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33744460905 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 33744460905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---