d00a6c8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 2.500s | 1.286ms | 20 | 20 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.660s | 16.333us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.770s | 34.155us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.080s | 1.102ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.850s | 405.870us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.530s | 131.293us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.770s | 34.155us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.850s | 405.870us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 3.900s | 5.245ms | 4 | 20 | 20.00 |
| V2 | disabled | rv_timer_disabled | 3.830s | 2.737ms | 20 | 20 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 13.668m | 3.269s | 10 | 10 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 13.668m | 3.269s | 10 | 10 | 100.00 |
| V2 | stress | rv_timer_stress_all | 8.590s | 6.576ms | 20 | 20 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.880s | 48.355us | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.800s | 19.672us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.260s | 601.367us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.260s | 601.367us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.660s | 16.333us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.770s | 34.155us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.850s | 405.870us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.950s | 34.846us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.660s | 16.333us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.770s | 34.155us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.850s | 405.870us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.950s | 34.846us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 194 | 210 | 92.38 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.930s | 76.342us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.400s | 380.515us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.400s | 380.515us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | min_value | rv_timer_min | 1.220s | 224.308us | 1 | 10 | 10.00 |
| V3 | max_value | rv_timer_max | 1.350s | 41.800us | 1 | 10 | 10.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 42.520s | 15.004ms | 14 | 20 | 70.00 |
| V3 | TOTAL | 16 | 40 | 40.00 | |||
| TOTAL | 310 | 350 | 88.57 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 25 failures:
0.rv_timer_min.103966871825601019646668090614941558993791118276946208171068866104712923070419
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 314250064 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc8a87304) == 0x1
UVM_INFO @ 314250064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_min.73928725140520855812876726615582132737273584506204894382307737000391943074248
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
UVM_FATAL @ 113595468 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x592f0b04) == 0x1
UVM_INFO @ 113595468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
2.rv_timer_random_reset.19951576732260049316119621559112660395137095681394707898658547570406493876007
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 176507615 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3d9dcb04) == 0x1
UVM_INFO @ 176507615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_timer_random_reset.12771649515037126915555798888057915812853095645707276881224631283151771922523
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1518193544 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xcf3bdd04) == 0x1
UVM_INFO @ 1518193544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
1.rv_timer_max.93556258205479133767378002079653808285030810990264340909898604992424345908800
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
UVM_ERROR @ 84628153 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 84628153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_max.58339372392458386825354342870731990223004330743498868645072140606818286356077
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_max/latest/run.log
UVM_ERROR @ 41799949 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 41799949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 5 failures:
1.rv_timer_stress_all_with_rand_reset.74774897114735414683597250673290145240629840313714225533853522712572295488476
Line 164, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2442083077 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 2442083077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_timer_stress_all_with_rand_reset.35232942986206235798302326809054997317517120560006600270249151692961903624380
Line 76, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/8.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13602054 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 13602054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
16.rv_timer_stress_all_with_rand_reset.79347015615586574951177024884649302867400014430600965247198833386271143427141
Line 76, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/16.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4445481 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 4445481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---