SPI_DEVICE/1R1W Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.466m	35.365ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.750s	23.878us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.090s	495.953us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	22.880s	2.269ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.330s	1.320ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.910s	122.302us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.090s	495.953us	20	20	100.00
		spi_device_csr_aliasing	18.330s	1.320ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.090s	12.424us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.470s	27.891us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.220s	33.497us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	3.316us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.930s	4.103us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	5.600s	184.306us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.600s	184.306us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.540s	17.237ms	50	50	100.00
		spi_device_tpm_sts_read	1.520s	95.955us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.890s	8.718ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.700s	52.364ms	50	50	100.00
		spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	28.390s	8.427ms	50	50	100.00
		spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	28.390s	8.427ms	50	50	100.00
		spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	27.970s	3.292ms	50	50	100.00
		spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	27.970s	3.292ms	50	50	100.00
		spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	27.970s	3.292ms	50	50	100.00
		spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	27.970s	3.292ms	50	50	100.00
		spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	27.970s	3.292ms	50	50	100.00
		spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	33.270s	7.134ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.706m	21.917ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.706m	21.917ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.706m	21.917ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	40.680s	40.620ms	50	50	100.00
		spi_device_read_buffer_direct	20.040s	4.785ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.706m	21.917ms	50	50	100.00
		spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	5.646m	351.725ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.720s	990.570us	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.720s	990.570us	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.466m	35.365ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.439m	1.016s	49	50	98.00
V2	stress_all	spi_device_stress_all	8.099m	587.987ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.140s	11.742us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.120s	39.565us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.500s	98.566us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.500s	98.566us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.750s	23.878us	5	5	100.00
		spi_device_csr_rw	3.090s	495.953us	20	20	100.00
		spi_device_csr_aliasing	18.330s	1.320ms	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	60.555us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.750s	23.878us	5	5	100.00
		spi_device_csr_rw	3.090s	495.953us	20	20	100.00
		spi_device_csr_aliasing	18.330s	1.320ms	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	60.555us	20	20	100.00
V2		TOTAL			938	961	97.61
V2S	tl_intg_err	spi_device_sec_cm	1.760s	556.592us	5	5	100.00
		spi_device_tl_intg_err	19.250s	1.071ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.250s	1.071ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.314m	50.433ms	49	50	98.00
		TOTAL			1127	1151	97.91

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.37531987802154981065087252329076742448460340836050686414812882203266218140487
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3141904 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[95])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3141904 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3141904 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[991])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.75652259564707168900535249856490424577472919508795205543764016152229931542227
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1033989 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[54])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1033989 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1033989 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[950])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 2 failures:

  • Test spi_device_flash_all has 1 failures.

    • 14.spi_device_flash_all.16983004616679386289152337897917608333894689670532290423429193208182478153762
      Line 74, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest/run.log

        UVM_ERROR @ 3719815803 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (14197760 [0xd8a400] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xd8a400 != exp 0x0
        UVM_INFO @ 3884359793 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 0/12
        UVM_INFO @ 3884359793 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 1/12
        UVM_INFO @ 5455825033 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/12
        UVM_INFO @ 5455825033 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/12
      

  • Test spi_device_flash_and_tpm_min_idle has 1 failures.

    • 32.spi_device_flash_and_tpm_min_idle.107941582605177212236787407911863537309981675838970278137248866749637280619337
      Line 90, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest/run.log

        UVM_ERROR @ 1362648444 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (16740352 [0xff7000] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xff7000 != exp 0x0
        tl_ul_fuzzy_flash_status_q[i] = 0x9a9148
        tl_ul_fuzzy_flash_status_q[i] = 0x16872e
        UVM_INFO @ 1445178396 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 5/11
        UVM_INFO @ 1575218123 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/8
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.97768312828534318686734506590763646012557577397599755692862162593558218365710
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1441900 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x28910e [1010001001000100001110] vs 0x0 [0])
        UVM_ERROR @   1467900 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf53397 [111101010011001110010111] vs 0x0 [0])
        UVM_ERROR @   1534900 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x548698 [10101001000011010011000] vs 0x0 [0])
        UVM_ERROR @   1549900 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfa0533 [111110100000010100110011] vs 0x0 [0])
        UVM_ERROR @   1568900 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5a4b27 [10110100100101100100111] vs 0x0 [0])
      

• Job timed out after * minutes has 1 failures:

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 18.spi_device_flash_mode_ignore_cmds.77406739661925464975961520462252681706541801778252787797150903439130416445395
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest/run.log

        Job timed out after 60 minutes