SPI_HOST Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.617m	2.741ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	34.000s	29.506us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	34.000s	31.434us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	36.000s	328.349us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	34.000s	90.416us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	34.000s	93.500us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	34.000s	31.434us	20	20	100.00
		spi_host_csr_aliasing	34.000s	90.416us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	34.000s	16.869us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	34.000s	82.745us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	2.000s	50.010us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	20.000s	535.991us	50	50	100.00
		spi_host_error_cmd	2.000s	46.557us	50	50	100.00
		spi_host_event	12.083m	29.418ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.000m	200.000ms	49	50	98.00
V2	speed	spi_host_speed	6.000m	200.000ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	6.000m	200.000ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	2.150m	6.505ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	139.279us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.000m	200.000ms	49	50	98.00
V2	full_cycle	spi_host_speed	6.000m	200.000ms	49	50	98.00
V2	duplex	spi_host_smoke	1.617m	2.741ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.617m	2.741ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.350m	7.196ms	50	50	100.00
V2	spien	spi_host_spien	6.483m	45.280ms	50	50	100.00
V2	stall	spi_host_status_stall	31.067m	1.000s	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	33.000s	6.466ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	20.000s	535.991us	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	44.139us	50	50	100.00
V2	intr_test	spi_host_intr_test	34.000s	14.873us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	35.000s	138.230us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	35.000s	138.230us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	34.000s	29.506us	5	5	100.00
		spi_host_csr_rw	34.000s	31.434us	20	20	100.00
		spi_host_csr_aliasing	34.000s	90.416us	5	5	100.00
		spi_host_same_csr_outstanding	34.000s	72.968us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	34.000s	29.506us	5	5	100.00
		spi_host_csr_rw	34.000s	31.434us	20	20	100.00
		spi_host_csr_aliasing	34.000s	90.416us	5	5	100.00
		spi_host_same_csr_outstanding	34.000s	72.968us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	35.000s	374.560us	20	20	100.00
		spi_host_sec_cm	2.000s	44.866us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	35.000s	374.560us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	9.733m	30.574ms	9	10	90.00
		TOTAL			837	840	99.64

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 1.spi_host_upper_range_clkdiv.10651824917888781422863875725031066006869180478152334266002478739847506924636
      Line 112, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_speed has 1 failures.

    • 13.spi_host_speed.90336262457650948804379432203657212066331705258957632694086818447952879793174
      Line 146, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/13.spi_host_speed/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_status_stall has 1 failures.

    • 42.spi_host_status_stall.37117486175776479609215906267096510140776406418168198207969126510956411882909
      Line 929, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/42.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---