SRAM_CTRL/MAIN Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.433m	513.861us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.050s	21.240us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.070s	16.068us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.470s	736.412us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.150s	123.005us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.870s	4.362ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.070s	16.068us	20	20	100.00
		sram_ctrl_csr_aliasing	1.150s	123.005us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.296m	35.899ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.347m	31.835ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	20.377m	22.526ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.998m	26.165ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	41.189m	442.788ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.911m	18.728ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.105m	296.274ms	50	50	100.00
V2	executable	sram_ctrl_executable	20.509m	28.987ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.538m	11.820ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.063m	31.797ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.759m	1.552ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.752m	801.674us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.972m	11.454ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	18.957m	69.479ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.680s	3.728ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.706h	2.278s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.110s	183.849us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.400s	49.723us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.400s	49.723us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.050s	21.240us	5	5	100.00
		sram_ctrl_csr_rw	1.070s	16.068us	20	20	100.00
		sram_ctrl_csr_aliasing	1.150s	123.005us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.210s	27.457us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.050s	21.240us	5	5	100.00
		sram_ctrl_csr_rw	1.070s	16.068us	20	20	100.00
		sram_ctrl_csr_aliasing	1.150s	123.005us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.210s	27.457us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.218m	7.217ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.980s	4.003us	0	5	0.00
		sram_ctrl_tl_intg_err	3.730s	2.280ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.980s	4.003us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.730s	2.280ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	18.957m	69.479ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	18.957m	69.479ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.070s	16.068us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	20.509m	28.987ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	20.509m	28.987ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	20.509m	28.987ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.105m	296.274ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	9.840s	2.678ms	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.218m	7.217ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.290s	6.574ms	35	50	70.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.433m	513.861us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.433m	513.861us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	20.509m	28.987ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.980s	4.003us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.105m	296.274ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.980s	4.003us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.980s	4.003us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.433m	513.861us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.980s	4.003us	0	5	0.00
V2S		TOTAL			121	145	83.45
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.521m	11.037ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1166	1190	97.98

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 15 failures:

  • Test sram_ctrl_readback_err has 15 failures.

    • 0.sram_ctrl_readback_err.27449925936075040129121758616181748345520835630395836848964842967079868775822
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2740191181 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4a) != exp (0x75)
        UVM_INFO @ 2740191181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.sram_ctrl_readback_err.74347707667445656287358433272802230641366322195255431372910638283907181614563
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2449680664 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6f) != exp (0x23)
        UVM_INFO @ 2449680664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 13 more failures.

• Offending 'reqfifo_rvalid' has 4 failures:

  • Test sram_ctrl_mubi_enc_err has 4 failures.

    • 13.sram_ctrl_mubi_enc_err.42598971501182735038234798591095943578823857804340289569729323428019823659904
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/13.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1370899152 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1370899152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 22.sram_ctrl_mubi_enc_err.36367454495915281487778843551560748943413739783584668556023555948486967640429
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/22.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2094262583 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2094262583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.32185123179664081320195382536355897062456441724582662542415594887969738120712
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7273022 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7273022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.47078364612663069970590719364451776771799977392719586420648000592372445031814
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12381310 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12381310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.31365055753297578788039769468013967966732085243631093720349411244001533683203
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4002791 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4002791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.15039612836024509567967846876343598460467001788951431282767916331662656779769
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3605096 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3605096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---