SRAM_CTRL/RET Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: `d00a6c8`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.775m	2.895ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.050s	16.607us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.050s	15.145us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.410s	1.663ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.110s	23.126us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.740s	146.928us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.050s	15.145us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	23.126us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	15.470s	7.337ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.640s	2.375ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	23.992m	22.423ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.819m	17.839ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.617m	23.587ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	22.917m	24.669ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.760s	4.067ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.289m	19.055ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.772m	218.334us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.243m	23.579ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.580m	721.576us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.671m	616.755us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.764m	302.696us	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.291m	11.099ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.210s	40.923us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.076h	53.344ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.050s	14.554us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.550s	159.726us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.550s	159.726us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.050s	16.607us	5	5	100.00
		sram_ctrl_csr_rw	1.050s	15.145us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	23.126us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.190s	77.547us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.050s	16.607us	5	5	100.00
		sram_ctrl_csr_rw	1.050s	15.145us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	23.126us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.190s	77.547us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.530s	1.676ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.010s	3.268us	0	5	0.00
		sram_ctrl_tl_intg_err	3.670s	4.979ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.010s	3.268us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.670s	4.979ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.291m	11.099ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.291m	11.099ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.050s	15.145us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.289m	19.055ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.289m	19.055ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.289m	19.055ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.760s	4.067ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.710s	175.783us	40	50	80.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.530s	1.676ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.580s	107.648us	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.775m	2.895ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.775m	2.895ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.289m	19.055ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.010s	3.268us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.760s	4.067ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.010s	3.268us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.010s	3.268us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.775m	2.895ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.010s	3.268us	0	5	0.00
V2S		TOTAL			120	145	82.76
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.359m	2.872ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1163	1190	97.73

Failure Buckets

Offending 'reqfifo_rvalid' has 10 failures:
- Test sram_ctrl_mubi_enc_err has 10 failures.
  - 15.sram_ctrl_mubi_enc_err.48212156490144696832465912199311769096255524556230537590581740161499188934479
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  32731466 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  32731466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 24.sram_ctrl_mubi_enc_err.115351934598609190815545714426326783334450582039225960762561971012831071511580
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  34372806 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  34372806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 9 failures:
- Test sram_ctrl_readback_err has 9 failures.
  - 2.sram_ctrl_readback_err.73890467552593696850345534511809957733981230952721295803215801850211257602634
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  25515437 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4b) != exp (0x26)
  UVM_INFO @  25515437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.sram_ctrl_readback_err.73522301840659112375175369057111721589844188598840793360235133392433342291982
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  42330193 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x26) != exp (0x14)
  UVM_INFO @  42330193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

0.sram_ctrl_sec_cm.37218535433207774772312039375433704012792060664380405602231793084555296914233
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @  20309351 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  20309351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.sram_ctrl_sec_cm.16513304815183546055633196802191346284692451680479263202468861851108800140158
Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @  10971023 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  10971023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(rdata_o))' has 2 failures:
- Test sram_ctrl_sec_cm has 2 failures.
  - 2.sram_ctrl_sec_cm.49489616173923391412511047300005876118516599325896827204059299358044054978068
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   4520600 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   4520600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.sram_ctrl_sec_cm.4654109663989672471199723055742901906231163069712604967666434734914979025877
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   3373007 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3373007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2730) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_readback_err has 1 failures.

1.sram_ctrl_readback_err.113865463512189561790149276814091187510586638735872542687102161389003844270239
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

  UVM_ERROR @  96851584 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2730) { a_addr: 'hb252b21c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h263aa  d_param: 'h0  d_source: 'h3c  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  96851584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test sram_ctrl_sec_cm has 1 failures.

3.sram_ctrl_sec_cm.99752127915470806883790375014088309826445860778870614437187297546678174981236
Line 103, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  UVM_ERROR @   3268016 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   3268016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.93123644808837449393672415898942039285388206060766400864769357009309988794479
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  59310240 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  59310240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 11.sram_ctrl_csr_mem_rw_with_rand_reset.62827200333075276198533098217534585417336195262428619777795755409435080605187
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 146928046 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 146928046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```