UART Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: `d00a6c8`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	22.340s	5.387ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	3.430s	1.034ms	5	5	100.00
V1	csr_rw	uart_csr_rw	1.010s	109.431us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.920s	253.396us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.060s	15.973us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.290s	71.250us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.010s	109.431us	20	20	100.00
		uart_csr_aliasing	1.060s	15.973us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.293m	109.927ms	50	50	100.00
V2	parity	uart_smoke	22.340s	5.387ms	50	50	100.00
		uart_tx_rx	3.293m	109.927ms	50	50	100.00
V2	parity_error	uart_intr	10.014m	370.224ms	50	50	100.00
		uart_rx_parity_err	5.654m	126.623ms	50	50	100.00
V2	watermark	uart_tx_rx	3.293m	109.927ms	50	50	100.00
		uart_intr	10.014m	370.224ms	50	50	100.00
V2	fifo_full	uart_fifo_full	9.893m	233.575ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.485m	221.924ms	49	50	98.00
V2	fifo_reset	uart_fifo_reset	6.747m	200.457ms	300	300	100.00
V2	rx_frame_err	uart_intr	10.014m	370.224ms	50	50	100.00
V2	rx_break_err	uart_intr	10.014m	370.224ms	50	50	100.00
V2	rx_timeout	uart_intr	10.014m	370.224ms	50	50	100.00
V2	perf	uart_perf	21.367m	28.457ms	50	50	100.00
V2	sys_loopback	uart_loopback	30.520s	11.502ms	50	50	100.00
V2	line_loopback	uart_loopback	30.520s	11.502ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	1.921m	51.229ms	9	50	18.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.193m	43.148ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	33.480s	6.321ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	50.010s	6.014ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	16.827m	179.508ms	50	50	100.00
V2	stress_all	uart_stress_all	23.325m	581.044ms	37	50	74.00
V2	alert_test	uart_alert_test	0.920s	45.502us	50	50	100.00
V2	intr_test	uart_intr_test	0.970s	82.183us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.740s	1.528ms	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.740s	1.528ms	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	3.430s	1.034ms	5	5	100.00
		uart_csr_rw	1.010s	109.431us	20	20	100.00
		uart_csr_aliasing	1.060s	15.973us	5	5	100.00
		uart_same_csr_outstanding	1.120s	113.870us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	3.430s	1.034ms	5	5	100.00
		uart_csr_rw	1.010s	109.431us	20	20	100.00
		uart_csr_aliasing	1.060s	15.973us	5	5	100.00
		uart_same_csr_outstanding	1.120s	113.870us	20	20	100.00
V2		TOTAL			1035	1090	94.95
V2S	tl_intg_err	uart_sec_cm	1.360s	66.516us	5	5	100.00
		uart_tl_intg_err	1.760s	89.101us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.760s	89.101us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.250m	9.747ms	81	100	81.00
V3		TOTAL			81	100	81.00
		TOTAL			1246	1320	94.39

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 33 failures:

Test uart_noise_filter has 18 failures.

0.uart_noise_filter.56838556529452586113716437564122025708811148691137317361981094722609889895266
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

  UVM_ERROR @  14745055 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 599359855 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 599436778 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 599513701 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 119 [0x77]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 688128997 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0

2.uart_noise_filter.20653970076193771061444263101365880990092197188176135769719318884151860592908
Line 75, in log /nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log

  UVM_ERROR @ 6401463978 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 6409235060 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 6410412181 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 6419058291 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 6425537665 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 16 more failures.

Test uart_stress_all_with_rand_reset has 11 failures.

4.uart_stress_all_with_rand_reset.37030435479507853289981444987320876295493807516553942193095792249600690801630
Line 84, in log /nightly/current_run/scratch/master/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 179128392 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 237321804 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 237332008 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 237342212 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_INFO @ 289800976 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/451

7.uart_stress_all_with_rand_reset.97640774398607462788883332503617428874813212629252985473856041576901734505848
Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  35059955 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  48059942 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  62059928 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 238982828 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 238982828 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1

... and 9 more failures.

Test uart_stress_all has 4 failures.

5.uart_stress_all.40647889635771725131198333867642368954295152348890890514206460628155234064182
Line 156, in log /nightly/current_run/scratch/master/uart-sim-vcs/5.uart_stress_all/latest/run.log

  UVM_ERROR @ 255061371551 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 255061371551 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 255777513692 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 5
  UVM_ERROR @ 255777561311 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 255777608930 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata

10.uart_stress_all.97522367208890745372264931444456606565812698057717508224901575030904117151582
Line 100, in log /nightly/current_run/scratch/master/uart-sim-vcs/10.uart_stress_all/latest/run.log

  UVM_ERROR @ 402828795808 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 402828795808 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 405747069154 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 405747069154 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 407726751658 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 2 more failures.

UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 22 failures:

Test uart_noise_filter has 14 failures.

1.uart_noise_filter.92348725308687277776003556408347739202607884167092413571557691396193483778613
Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log

  UVM_ERROR @ 2044362469 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 12,                                 clk_pulses: 0
  UVM_ERROR @ 2044372886 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 2044383303 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (183 [0xb7] vs 249 [0xf9]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 2118187748 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 2118187748 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

3.uart_noise_filter.109043014048561819398037303602986511780385057201243647852816253136566164412825
Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/3.uart_noise_filter/latest/run.log

  UVM_ERROR @ 29431566907 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
  UVM_ERROR @ 29431638336 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 29431709765 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 29431781194 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 29431852623 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata

... and 12 more failures.

Test uart_stress_all has 4 failures.

4.uart_stress_all.15844578717913544438634692953185531994173440136466726516780380371455764866898
Line 81, in log /nightly/current_run/scratch/master/uart-sim-vcs/4.uart_stress_all/latest/run.log

  UVM_ERROR @ 32605871878 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7,                                 clk_pulses: 0
  UVM_ERROR @ 32605883114 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 32605973002 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (192 [0xc0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 32607995482 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
  UVM_ERROR @ 32608006718 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

7.uart_stress_all.45576456193581236557875379994397564579985442910085683676051171098602515797319
Line 84, in log /nightly/current_run/scratch/master/uart-sim-vcs/7.uart_stress_all/latest/run.log

  UVM_ERROR @ 25505676023 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 25505697762 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 25505719501 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (29 [0x1d] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 25570001724 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 25570001724 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 2 more failures.

Test uart_stress_all_with_rand_reset has 4 failures.

14.uart_stress_all_with_rand_reset.71506568834499020499937324990518470517644749456412476460296768392875273744021
Line 91, in log /nightly/current_run/scratch/master/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 682669336 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0
  UVM_ERROR @ 682679437 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 682689538 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (41 [0x29] vs 127 [0x7f]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 682709740 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0
  UVM_ERROR @ 682719841 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

15.uart_stress_all_with_rand_reset.60118656482557888587038098429200576865561607281071178680925166895952130551788
Line 108, in log /nightly/current_run/scratch/master/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 950438310 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 950790435 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 950832690 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 961142910 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_INFO @ 1085400780 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/707

... and 2 more failures.

UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 11 failures:

Test uart_noise_filter has 6 failures.

8.uart_noise_filter.97395086135509902865963439133373538321852809007186907986270067831767221072348
Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log

  UVM_ERROR @ 73544656704 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 73544656704 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 74046988028 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7,                                 clk_pulses: 0
  UVM_ERROR @ 74047071361 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 74047154694 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (86 [0x56] vs 223 [0xdf]) reg name: uart_reg_block.rdata

12.uart_noise_filter.102594668662961870767555039730747766380489720895054265113887074590622524395020
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/12.uart_noise_filter/latest/run.log

  UVM_ERROR @ 178743245 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 178743245 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 187823245 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 193843245 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 194303245 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0

... and 4 more failures.

Test uart_stress_all has 5 failures.

32.uart_stress_all.89725263443074535601774815243266108147011286426502789193449003956385255189483
Line 90, in log /nightly/current_run/scratch/master/uart-sim-vcs/32.uart_stress_all/latest/run.log

  UVM_ERROR @ 9649293809 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 9649293809 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 9649293809 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 9808217353 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 9808237971 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (34 [0x22] vs 255 [0xff]) reg name: uart_reg_block.rdata

35.uart_stress_all.82126205353949700635491102855635248260418144259503089952697355357397188128238
Line 90, in log /nightly/current_run/scratch/master/uart-sim-vcs/35.uart_stress_all/latest/run.log

  UVM_ERROR @ 94485212065 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 94485212065 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 94485212065 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 94514464561 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 94514464561 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr

... and 3 more failures.

UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 3 failures:

Test uart_noise_filter has 1 failures.

20.uart_noise_filter.74054836825904461388792953807856335513905385429905654807634249306482405520631
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/20.uart_noise_filter/latest/run.log

  UVM_ERROR @   1430660 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 17021020660 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/17
  UVM_ERROR @ 17032520660 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 17041320660 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 17042000660 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

Test uart_fifo_overflow has 1 failures.

44.uart_fifo_overflow.4349692013975819092151337913534980698447755922840011993757822493936150298652
Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/44.uart_fifo_overflow/latest/run.log

  UVM_ERROR @  55550575 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 199200575 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/6
  UVM_INFO @ 13552110575 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/6
  UVM_INFO @ 13685540575 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/6
  UVM_INFO @ 22897260575 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 5/6

Test uart_stress_all_with_rand_reset has 1 failures.

56.uart_stress_all_with_rand_reset.90456781518645704698051060184400332782473004019210510970244220438908890239716
Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   1260996 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @  10406868 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @  10500621 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/10

UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 3 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

36.uart_stress_all_with_rand_reset.58033458370906018524468693839392124874101554676515191555822525637273955338734
Line 146, in log /nightly/current_run/scratch/master/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1933601208 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 1960695825 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 1960695825 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 1976613001 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
  UVM_ERROR @ 1976623418 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

Test uart_noise_filter has 2 failures.

43.uart_noise_filter.90824721043871114803725996340683719309752887619468167060954926916530055127606
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/43.uart_noise_filter/latest/run.log

  UVM_ERROR @ 132090371 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 132090371 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @ 261171639 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 261171639 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @ 263004943 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr

49.uart_noise_filter.38798803107729054811716007688033479376906204785731791866522896711616353449506
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/49.uart_noise_filter/latest/run.log

  UVM_ERROR @ 121933437 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 121933437 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @ 371045575 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 371045575 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 634293582 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 4,                                 clk_pulses: 0

UVM_ERROR (cip_base_vseq.sv:1142) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

57.uart_stress_all_with_rand_reset.95636421082359714266781107534393006046590468019109839161440937386049926946867
Line 131, in log /nightly/current_run/scratch/master/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5716118157 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5716118157 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/5
  UVM_INFO @ 5716409826 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/5

UVM_ERROR (cip_base_vseq.sv:1229) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

94.uart_stress_all_with_rand_reset.101640653216820593163957290933550282201117905427820037752154263974810486154495
Line 98, in log /nightly/current_run/scratch/master/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4263960181 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4263988140 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4263988140 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 4264001848 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1