CHIP Simulation Results

Friday October 31 2025 17:07:40 UTC

GitHub Revision: d00a6c8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	3.288m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	3.288m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.949m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	2.071m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	2.308m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.814m	6.600ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.814m	6.600ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.814m	6.600ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	37.780s	10.300us	0	3	0.00
		chip_sw_example_manufacturer	3.562m		0	3	0.00
		chip_sw_example_concurrency	6.756m	5.423ms	3	3	100.00
		chip_sw_uart_smoketest_signed	18.901s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	16.280s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	14.440s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	14.440s		0	3	0.00
V1	xbar_smoke	xbar_smoke	36.130s	68.886us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.804m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.587m	9.295ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	7.434m	5.154ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.575m		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.424m		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.272m		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.686m		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.820s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.820s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.595m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.546m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	3.421m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	3.421m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.982m	5.120ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	4.179m	4.223ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	9.927m	8.879ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	20.224s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	18.303s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	21.907m	26.856ms	1	3	33.33
V2	chip_sw_timer	chip_sw_rv_timer_irq	8.644m	5.477ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	39.656m	18.027ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	39.656m	18.027ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	16.641s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.437m	4.886ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.437m	4.886ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.297m	18.019ms	0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.893m	5.691ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.632m	5.352ms	3	3	100.00
		chip_sw_aes_idle	7.212m	5.074ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.119m	5.330ms	3	3	100.00
		chip_sw_kmac_idle	5.001m	3.336ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	23.532m	12.019ms	0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	24.322m	12.018ms	0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	20.774m	12.027ms	0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	20.979m	12.019ms	0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	18.417s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.770s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	19.210s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.850s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.696s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	19.826s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.471s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.417s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.770s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	19.210s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.850s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.696s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	19.826s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.471s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	53.880s	10.240us	0	3	0.00
		chip_sw_aes_enc_jitter_en	59.360s	10.320us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.052m	10.140us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	59.040s	10.220us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.006m	10.200us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.655s		0	3	0.00
		chip_sw_clkmgr_jitter	5.836m	5.542ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.758m	4.320ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	56.810s	10.300us	0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	49.840s	10.120us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	52.300s	10.220us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	54.110s	10.300us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	48.910s	10.260us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.059m	10.320us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	18.256s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.450s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	19.594s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	20.725s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	36.509m	15.721ms	83	100	83.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	12.956m	12.972ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	7.437m	4.886ms	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	20.034s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	12.956m	12.972ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	20.047s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	19.105s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	26.784s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	58.781s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	23.319s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	36.509m	15.721ms	83	100	83.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	9.927m	8.879ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	41.129m	20.027ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.313m	7.274ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.971m	10.479ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	6.274m	4.265ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	36.509m	15.721ms	83	100	83.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	21.501s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	19.636s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	36.509m	15.721ms	83	100	83.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	17.967s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.971m	10.479ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	19.103s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	20.869s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	18.051s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	19.958s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.020s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	18.762s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	19.636s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	21.364s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	51.243s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.364s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.364s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.364s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	12.292m	9.645ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	26.245s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	26.387s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	26.298s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	20.388s		0	3	0.00
		chip_sw_lc_ctrl_transition	21.364s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	11.756m	9.738ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	14.394m	12.439ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	19.960s		0	3	0.00
		chip_prim_tl_access	21.286m	21.216ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.417s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	18.770s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	19.210s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.850s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.696s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	19.826s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.471s		0	3	0.00
		chip_rv_dm_lc_disabled	21.907m	26.856ms	1	3	33.33
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.383m	5.004ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	59.360s	10.320us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.326m	4.090ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	7.212m	5.074ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.531m	5.612ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	1.052m	10.140us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.119m	5.330ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	6.290m	5.347ms	3	3	100.00
		chip_sw_kmac_mode_kmac	8.193m	5.803ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.006m	10.200us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	11.756m	9.738ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.364s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	51.650s	10.360us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	7.513m	4.557ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.001m	3.336ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.442m	5.321ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.442m	5.321ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	30.266s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	7.054m	5.609ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	18.733s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	11.756m	9.738ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	59.040s	10.220us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	1.309h	17.186ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.880s	10.240us	0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.632m	5.352ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.632m	5.352ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.632m	5.352ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	11.259m	5.549ms	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	14.394m	12.439ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	14.394m	12.439ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.063m	9.287ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.655s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	19.960s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	36.509m	15.721ms	83	100	83.00
		chip_sw_data_integrity_escalation	3.421m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.364s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	11.259m	5.549ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	11.756m	9.738ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	13.063m	9.287ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	7.159m	5.598ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	11.259m	5.549ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	11.756m	9.738ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	13.063m	9.287ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	7.159m	5.598ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.364s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	21.278s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	51.243s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	26.245s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	26.387s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	26.298s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	20.388s		0	3	0.00
		chip_sw_lc_ctrl_transition	21.364s		0	15	0.00
		chip_prim_tl_access	21.286m	21.216ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	21.286m	21.216ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	14.858s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	16.081s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.450s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	53.880s	10.240us	0	3	0.00
		chip_sw_aes_enc_jitter_en	59.360s	10.320us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.052m	10.140us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	59.040s	10.220us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.006m	10.200us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.655s		0	3	0.00
		chip_sw_clkmgr_jitter	5.836m	5.542ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	10.999m	9.026ms	3	3	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	10.999m	9.026ms	3	3	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	6.601m	4.173ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	6.227m	5.464ms	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.143m	4.926ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	10.488m	5.170ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.065m	4.376ms	2	3	66.67
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.929m	4.496ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	7.159m	5.598ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	41.129m	20.027ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	41.129m	20.027ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	5.751m	5.456ms	3	3	100.00
		chip_sw_aon_timer_smoketest	7.716m	4.748ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.311m	4.281ms	3	3	100.00
		chip_sw_csrng_smoketest	5.333m	4.425ms	3	3	100.00
		chip_sw_gpio_smoketest	6.434m	5.571ms	3	3	100.00
		chip_sw_hmac_smoketest	6.508m	5.663ms	3	3	100.00
		chip_sw_kmac_smoketest	7.666m	5.872ms	3	3	100.00
		chip_sw_otbn_smoketest	6.789m	4.578ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	6.186m	4.887ms	3	3	100.00
		chip_sw_rv_plic_smoketest	6.729m	5.545ms	3	3	100.00
		chip_sw_rv_timer_smoketest	7.843m	4.821ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.503m	4.145ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	7.494m	5.664ms	3	3	100.00
		chip_sw_uart_smoketest	6.803m	5.447ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	18.565s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	18.901s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.804m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	18.631s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.866m	5.858ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	5.034m	5.466ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.845m	4.954ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	6.726m	4.511ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	26.416s		0	3	0.00
		chip_rv_dm_lc_disabled	21.907m	26.856ms	1	3	33.33
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	19.457s		0	3	0.00
		chip_sw_lc_walkthrough_prod	18.325s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	21.671s		0	3	0.00
		chip_sw_lc_walkthrough_rma	19.516s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	26.416s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.810m	10.381ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	10.044m	9.466ms	3	3	100.00
		rom_volatile_raw_unlock	17.033s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	18.007s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.379m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.678m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	5.814m	5.371ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	5.814m	5.371ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	14.440s		0	3	0.00
		chip_same_csr_outstanding	15.840s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	14.440s		0	3	0.00
		chip_same_csr_outstanding	15.840s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	5.036m	492.312us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	14.970s	13.054us	100	100	100.00
		xbar_smoke_large_delays	9.007m	2.700ms	100	100	100.00
		xbar_smoke_slow_rsp	9.979m	2.047ms	100	100	100.00
		xbar_random_zero_delays	2.273m	76.068us	100	100	100.00
		xbar_random_large_delays	35.173m	11.400ms	100	100	100.00
		xbar_random_slow_rsp	49.172m	13.562ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	3.036m	238.779us	100	100	100.00
		xbar_error_and_unmapped_addr	2.516m	220.277us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	4.576m	473.738us	100	100	100.00
		xbar_error_and_unmapped_addr	2.516m	220.277us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	7.489m	921.932us	100	100	100.00
		xbar_access_same_device_slow_rsp	59.016m	16.867ms	74	100	74.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.917m	447.748us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	33.527m	3.974ms	100	100	100.00
		xbar_stress_all_with_error	29.767m	4.292ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	55.048m	5.143ms	98	100	98.00
		xbar_stress_all_with_reset_error	58.143m	7.322ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	18.644s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	18.113s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	17.460s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	17.602s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	14.350s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	14.636s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	18.366s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	15.752s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.143s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.340s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.485s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	15.039s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	15.893s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.193m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.110m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.512m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.409m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.503m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.150m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.238m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.400m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	59.657s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.152m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	51.403s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	59.627s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	53.128s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	45.286s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	41.763s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.202s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.762s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.195s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.694s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.449s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	18.497s		0	3	0.00
		rom_e2e_asm_init_dev	17.547s		0	3	0.00
		rom_e2e_asm_init_prod	18.235s		0	3	0.00
		rom_e2e_asm_init_prod_end	19.539s		0	3	0.00
		rom_e2e_asm_init_rma	18.622s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	18.823s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	19.090s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	18.314s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	17.205s		0	3	0.00
V2		TOTAL			1902	2429	78.30
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	7.134m	5.595ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	5.271m	4.488ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.133s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.135s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.049s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	18.357s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	36.509m	15.721ms	83	100	83.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	18.814s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.202m	4.609ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	17.444s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	19.025s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.133s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.135s		0	1	0.00
		rom_e2e_jtag_debug_rma	14.049s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	17.380s		0	1	0.00
		rom_e2e_jtag_inject_dev	17.454s		0	1	0.00
		rom_e2e_jtag_inject_rma	14.492s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	16.304s		0	3	0.00
V3		TOTAL			0	20	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	38.237m	16.495ms	3	3	100.00
		chip_sw_entropy_src_kat_test	6.455m	5.682ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.047m	4.234ms	3	3	100.00
		chip_plic_all_irqs_0	13.681m	5.736ms	3	3	100.00
		chip_plic_all_irqs_10	14.740m	6.228ms	3	3	100.00
		chip_sw_dma_inline_hashing	6.923m	4.517ms	3	3	100.00
		chip_sw_dma_abort	6.260m	4.256ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	18.597s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	18.851s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	14.856s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	16.346s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	18.944s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	17.802s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	17.049s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	16.419s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	17.787s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	18.377s		0	3	0.00
		chip_sw_entropy_src_smoketest	9.594m	5.596ms	3	3	100.00
		chip_sw_mbx_smoketest	8.504m	5.788ms	3	3	100.00
		TOTAL			2038	2668	76.39

Failure Buckets

• Job returned non-zero exit code has 437 failures:

  • Test chip_sw_example_manufacturer has 3 failures.

    • 0.chip_sw_example_manufacturer.101732278733112446277133484015892243712755950584257221073436727832631095885172
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

        Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 193.815s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_example_manufacturer.46329545474699809198529009132197799299879885048126505626387055384975321985388
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

        Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 10.250s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_data_integrity_escalation has 6 failures.

    • 0.chip_sw_data_integrity_escalation.42844600337837099673689249824509063706442133963194515428808372040341925393948
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

        Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 186.263s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_data_integrity_escalation.111428876156019106453305791343621438047287512290081775644906474291428275370407
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

        Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 3.239s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 4 more failures.

  • Test chip_sw_sleep_pin_wake has 3 failures.

    • 0.chip_sw_sleep_pin_wake.22617562724340190234759965279923986523313145979363317720333933477899195680798
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 137.280s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_sleep_pin_wake.103723146950583028155559003141821676865206843977583782292319035029983368240523
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 17.720s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_sleep_pin_retention has 3 failures.

    • 0.chip_sw_sleep_pin_retention.37713888131917480478324371332078653693600183377099178661717034151835332944678
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

        Target //sw/device/tests:sleep_pin_retention_test_sim_dv failed to build
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 136.647s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_sleep_pin_retention.7262523550164790016463784901449807479818448576761203998850508386468065839811
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 3.663s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_uart_tx_rx has 5 failures.

    • 0.chip_sw_uart_tx_rx.115635194323482204687369601580268974001615167160428069416094761767912742433989
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

        Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 180.626s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_uart_tx_rx.92949740510962238169911073709122961887290531260445176340765517820604016383533
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log

        Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 7.200s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 3 more failures.

  • ... and 125 more tests.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 33 failures:

  • Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 3 failures.

    • 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.52777702212312109085288024482728573463463006935339730182925632089144824118329
      Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log

        UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.36642750154963467767833225490347775929260953160172219581688549772052493279586
      Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log

        UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_aes_enc_jitter_en has 3 failures.

    • 0.chip_sw_aes_enc_jitter_en.17408331275217139599020140368229559895348364125816747306789841503789081617711
      Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aes_enc_jitter_en.106372054247733705981834671221741982791511961647255517259331021614581355057353
      Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_hmac_enc_jitter_en has 3 failures.

    • 0.chip_sw_hmac_enc_jitter_en.33364382860170724977847933743971058954238987477755043787869314844843710010944
      Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_hmac_enc_jitter_en.10005454193440720057387790675147098130174048342916565864968710020308272275422
      Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.75329709626581884561485688903435058083367590887459818985077878193595398570533
      Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.53931311299505870147275109779814170097409897134893692566256757933225418436316
      Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.

    • 0.chip_sw_kmac_mode_kmac_jitter_en.109941144883030350894406816171762942496600062573822336488142291223845875807280
      Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

        UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_kmac_mode_kmac_jitter_en.78100677818054848966632791157711253652964827373496964313132651101399148599481
      Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

        UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • ... and 6 more tests.

• Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 28 failures:

  • Test chip_tl_errors has 28 failures.

    • 0.chip_tl_errors.52325035270913386660381444044863401277428175018889879246134460539628851216985
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

            Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
        UVM_ERROR @ 3021.851722 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
        UVM_INFO @ 3021.851722 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_tl_errors.74577426801755670513915780050946876319075873718581599283513810573564714336342
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log

            Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
        UVM_ERROR @ 3357.816528 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
        UVM_INFO @ 3357.816528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 26 more failures.

• Job timed out after * minutes has 28 failures:

  • Test xbar_access_same_device_slow_rsp has 26 failures.

    • 10.xbar_access_same_device_slow_rsp.102564823391954931167700884430357049746035159107247686301043784632323229519191
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest/run.log

        Job timed out after 60 minutes
      

    • 15.xbar_access_same_device_slow_rsp.17676027804240253795295557375975832120467982631596854637830081580279362285008
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.xbar_access_same_device_slow_rsp/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 24 more failures.

  • Test xbar_stress_all_with_rand_reset has 2 failures.

    • 20.xbar_stress_all_with_rand_reset.6160234497838784923245556382330185615574846056989668333506728457445278641780
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/20.xbar_stress_all_with_rand_reset/latest/run.log

        Job timed out after 60 minutes
      

    • 40.xbar_stress_all_with_rand_reset.86804715079686235492151597968896676818578786192051460575731911307218382563630
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/40.xbar_stress_all_with_rand_reset/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 11 failures:

  • Test chip_sw_rstmgr_cpu_info has 3 failures.

    • 0.chip_sw_rstmgr_cpu_info.112547961107543573692742907248840079012858633953357062524499213106960629435496
      Line 447, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

        UVM_ERROR @ 20018.530901 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns
      
        UVM_INFO @ 20018.530901 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_rstmgr_cpu_info.76371465031250722650991924976257249130201405670965971861483974510199355852725
      Line 426, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

        UVM_ERROR @ 20018.659552 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns
      
        UVM_INFO @ 20018.659552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_aon_timer_irq has 3 failures.

    • 0.chip_sw_aon_timer_irq.62393034732117518705320495203669072225485211382755240864179772312267054296421
      Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

        UVM_ERROR @ 18018.676843 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18018.676843 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aon_timer_irq.45321097242361933652048654994226383058137977651154316199913223168998746347099
      Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

        UVM_ERROR @ 18018.438924 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18018.438924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 5 failures.

    • 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.48550318139274884346121532706072670599409496651366787782422059367642087744439
      Line 419, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

        UVM_ERROR @ 18018.695917 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18018.695917 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.34192720273204708884240033459903440615400588311101226001529833568826945253990
      Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

        UVM_ERROR @ 18018.678082 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18018.678082 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 11 failures:

  • Test chip_sw_clkmgr_off_aes_trans has 2 failures.

    • 0.chip_sw_clkmgr_off_aes_trans.25146666862175589383636477528131389634622495070007635911980300120419051068126
      Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

        UVM_ERROR @ 12018.423998 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.423998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_aes_trans.65622311644319922898526817770865863072266742266300304652971235653281254116026
      Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log

        UVM_ERROR @ 12018.504718 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.504718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_hmac_trans has 3 failures.

    • 0.chip_sw_clkmgr_off_hmac_trans.79484371866375872784689880965501729466728812155133833181864381150528904090445
      Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

        UVM_ERROR @ 12018.479341 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.479341 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_hmac_trans.25817314686478331080366520612728812341341427970876133157647005001644912804587
      Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log

        UVM_ERROR @ 12018.422594 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.422594 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_clkmgr_off_kmac_trans has 3 failures.

    • 0.chip_sw_clkmgr_off_kmac_trans.56887326489023160856757453407775303733110646454592724966580234312847069987353
      Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

        UVM_ERROR @ 12026.983381 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.983381 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_kmac_trans.12301733626904130523266453370040544445880619796750923053257594270517788198244
      Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log

        UVM_ERROR @ 12026.903236 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.903236 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_clkmgr_off_otbn_trans has 3 failures.

    • 0.chip_sw_clkmgr_off_otbn_trans.26619775710417521509018458494232168913187168335694431099341809354500695867708
      Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

        UVM_ERROR @ 12026.763773 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.763773 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_otbn_trans.6825870788262896225982135483358548245503078189637170785036437087954944377886
      Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log

        UVM_ERROR @ 12018.632500 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.632500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:

  • Test chip_padctrl_attributes has 10 failures.

    • 0.chip_padctrl_attributes.42003910749835465424650796024624383687156822881935525209240606209644992967265
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

    • 1.chip_padctrl_attributes.82727682127673359558940480393649174010883415766832646356314670188721790226207
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

    • ... and 8 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:

  • Test chip_csr_bit_bash has 3 failures.

    • 0.chip_csr_bit_bash.58083067550679553295204623070273728087083681026816430074025185116487093398620
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_csr_bit_bash.110504904619380866287465350285076044198204418354154266609437564334205606041767
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_csr_aliasing has 3 failures.

    • 0.chip_csr_aliasing.11981281569754465201306173990078830828217194191084592673959996503582323448164
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_csr_aliasing.28779768561384530958294816018009855972432960972226179260422899039880452633491
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_same_csr_outstanding has 3 failures.

    • 0.chip_same_csr_outstanding.51343531643382893322072457310969049954527019654665120290472131420884527087847
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_same_csr_outstanding.80799642773996424250675322899574058545612421451926391434605322095942081869548
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 6 failures:

  • Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation.15432420411789077958584145720938027039869173828001708091552033058038788433808
      Line 423, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

        UVM_ERROR @ 5762.608452 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (2481625845663590485613384304939770039305231689255529276117804374236052019770381183002049225918193162357988136428364002017725464579210695060318436907637852 [0x2f61ef38aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3a9375fc97f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 5762.608452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_keymgr_dpe_key_derivation.95713725603353394316341617669644348426260458882166857474124573917372337444476
      Line 417, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

        UVM_ERROR @ 9737.511184 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (8208477588273908141712902905255760060385569397666022890181712424981274391364719929915928203168107284482295689750684894083694785632197716781791338624801884 [0x9cba33e2aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd31aec83137f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 9737.511184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation_prod.105998019216605870278820705862973868991355916736742797566124928793316214163456
      Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

        UVM_ERROR @ 7038.192280 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6863051366839452038329468028768839791838276390640216691748341571681171083203245177775273639377258739780890014737771906138689023013207420913906503844715612 [0x8309e573aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3055f55827f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 7038.192280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_keymgr_dpe_key_derivation_prod.29199914915722518345776672034855634517979439445107176494202286106471574066638
      Line 432, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

        UVM_ERROR @ 9644.738640 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (899982889575197105206427061833095930315417769339707914118675009086674514719296329827910940582512730180112831416672703675676285220474196728312737418271836 [0x112f0654aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd39779b6a57f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 9644.738640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47297) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

  • Test chip_jtag_csr_rw has 3 failures.

    • 0.chip_jtag_csr_rw.7700538313593357896768398639184770168893317152974570548401417238647621012571
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 3315.932928 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47297) { a_addr: 'h30480000  a_data: 'hb48a35a6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc  a_opcode: 'h1  a_user: 'h248a7  d_param: 'h0  d_source: 'hc  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3315.932928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_jtag_csr_rw.113333338444158741908214932056523344883265292739560705285710804706767132549345
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 4936.592247 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47297) { a_addr: 'h30480000  a_data: 'h7d7c8f5a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3e  a_opcode: 'h0  a_user: 'h26967  d_param: 'h0  d_source: 'h3e  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 4936.592247 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_jtag_mem_access has 3 failures.

    • 0.chip_jtag_mem_access.114883792476656391356678313306540975230056588131001186731205224806457220053327
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 2930.192923 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47297) { a_addr: 'h30480000  a_data: 'h98843833  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h0  a_user: 'h26968  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2930.192923 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_jtag_mem_access.41306559575121786039288067731248494280672346259851156121973392585378929702765
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 5456.433114 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47297) { a_addr: 'h30480000  a_data: 'h152d6fb2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h0  a_user: 'h26909  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 5456.433114 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 5 failures:

  • Test chip_sw_otp_ctrl_escalation has 1 failures.

    • 0.chip_sw_otp_ctrl_escalation.80902631496784128311670330061918472572196292773287709520496304333378291740145
      Line 451, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 4609.200676 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 4609.200676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_all_escalation_resets has 4 failures.

    • 1.chip_sw_all_escalation_resets.62041077072265089268041515666023737603702707529683379967448389385729577620292
      Line 478, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 4459.226032 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 4459.226032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.chip_sw_all_escalation_resets.102117880987546072239089061251214452141712243371694945557551959074139601191251
      Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log

            Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
        UVM_ERROR @ 5571.000624 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
        UVM_INFO @ 5571.000624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 4 failures:

  • Test chip_sw_all_escalation_resets has 4 failures.

    • 15.chip_sw_all_escalation_resets.10181322253307764469840068804881011883985821701472197597241744217316399776786
      Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 5479.153414 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
        UVM_INFO @ 5479.153414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 77.chip_sw_all_escalation_resets.77823567387060489878780130661450372691642175031779833449608493616939289425477
      Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 5420.953894 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
        UVM_INFO @ 5420.953894 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:

  • Test chip_sw_example_rom has 3 failures.

    • 0.chip_sw_example_rom.5918591313922972388643551336504874152233332683159130189127484780637670818954
      Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

        UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
        UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_example_rom.23583295603637616771705140898769468217076812738487823247132355914436853503561
      Line 449, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log

        UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
        UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:

  • Test chip_sw_spi_device_pass_through_collision has 3 failures.

    • 0.chip_sw_spi_device_pass_through_collision.46589623118229549565279448694752844405631974915905753529320332680808399732520
      Line 432, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 5153.969912 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 5153.969912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_spi_device_pass_through_collision.112453766245613963090600180280559037985309853992242861203809125740661911053699
      Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 3896.813292 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 3896.813292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 3 failures:

  • Test chip_sw_rstmgr_alert_info has 3 failures.

    • 0.chip_sw_rstmgr_alert_info.100586209107677091920176167067954593369094192366315511238794408744982671271444
      Line 696, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

        UVM_ERROR @ 10478.605384 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
        UVM_INFO @ 10478.605384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_rstmgr_alert_info.106056901491534950928326994154434337210322176826051602201128028097497057856299
      Line 640, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log

        UVM_ERROR @ 7099.822744 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
        UVM_INFO @ 7099.822744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

  • Test chip_sw_soc_proxy_external_alerts has 3 failures.

    • 0.chip_sw_soc_proxy_external_alerts.108875816670500073118038975547291079629849331840866756509400235392053880876124
      Line 438, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

        UVM_ERROR @ 5379.535632 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
        UVM_INFO @ 5379.535632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_soc_proxy_external_alerts.15940025376185437458391433202263480955079604797648295681932005221870558965530
      Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

        UVM_ERROR @ 4173.073042 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
        UVM_INFO @ 4173.073042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:

  • Test chip_sw_soc_proxy_external_wakeup has 3 failures.

    • 0.chip_sw_soc_proxy_external_wakeup.17073802342699272936716226334075071280423598679768184962764710176394288992735
      Line 429, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log

        UVM_ERROR @ 4697.498880 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
        UVM_INFO @ 4697.498880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_soc_proxy_external_wakeup.102826381673589372664606142227487468148965676024256619205014698164716760483586
      Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log

        UVM_ERROR @ 3980.537141 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
        UVM_INFO @ 3980.537141 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:

  • Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.

    • 0.chip_sw_aon_timer_wdog_bite_reset.74591392737702791144127448861624353089965135409838333117645110667731348830845
      Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log

        UVM_ERROR @ 4886.352804 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
        UVM_INFO @ 4886.352804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aon_timer_wdog_bite_reset.52466625304847554154358775889580086738941963311101604644205494783885074762172
      Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log

        UVM_ERROR @ 5369.618155 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
        UVM_INFO @ 5369.618155 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:

  • Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.

    • 0.chip_sw_rv_core_ibex_nmi_irq.101105391624253969678360060200017025940266506038320361064036028998048603683361
      Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log

        UVM_ERROR @ 5169.834475 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
        UVM_INFO @ 5169.834475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_rv_core_ibex_nmi_irq.111720034159368347261214704487776899209060818743427419418983382468473990531533
      Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log

        UVM_ERROR @ 6639.337635 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
        UVM_INFO @ 6639.337635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:

  • Test chip_sw_kmac_app_rom has 3 failures.

    • 0.chip_sw_kmac_app_rom.83547570259996759550307541128135160594212854035043216102770922736734291477275
      Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log

        UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_kmac_app_rom.69088985254727462022894025507130677347212964571588705038866425673449886029299
      Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log

        UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

  • Test chip_sw_dma_abort has 3 failures.

    • 0.chip_sw_dma_abort.21962807215619300497741606161973540599357775963521372408171040842089432769982
      Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

        UVM_FATAL @ 5282.769576 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
        UVM_INFO @ 5282.769576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_dma_abort.88392543778661334320097009515916418071059401900882446730772280940967989937598
      Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

        UVM_FATAL @ 4734.920584 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
        UVM_INFO @ 4734.920584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

  • Test chip_sw_all_escalation_resets has 3 failures.

    • 19.chip_sw_all_escalation_resets.1101342204115212302089175766122563524401731035502962813589155970221128203809
      Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 12018.650583 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.650583 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 32.chip_sw_all_escalation_resets.84249452633786705537763136581279846963957628291761637763723384501745118240464
      Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 12018.552630 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.552630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:

  • Test chip_sw_all_escalation_resets has 3 failures.

    • 52.chip_sw_all_escalation_resets.101825431137683483146340744215286840950655144219438264964865724371832152682797
      Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 4925.023280 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
        UVM_INFO @ 4925.023280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 72.chip_sw_all_escalation_resets.4947458738943847565095654403714101863751726503286263653406372209741636832918
      Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 5740.132688 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
        UVM_INFO @ 5740.132688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 3 failures:

  • Test chip_sw_all_escalation_resets has 3 failures.

    • 75.chip_sw_all_escalation_resets.46269605586729877407967010630291044403170149173542584377938502611570678343479
      Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest/run.log

        UVM_FATAL @  10.360001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 82.chip_sw_all_escalation_resets.49032284176750479692463278724157210900687899881645481243607764938434184277238
      Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest/run.log

        UVM_FATAL @  10.360001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:

  • Test chip_rv_dm_lc_disabled has 2 failures.

    • 0.chip_rv_dm_lc_disabled.82198221133552591722758518168102681865768327684116690171868671072765355267323
      Line 233, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

        UVM_ERROR @ 11817.556718 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40718 read out mismatch
        UVM_INFO @ 11817.556718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_rv_dm_lc_disabled.89155249716884699727611906021502566117190110066806862842697966775718139768755
      Line 257, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log

        UVM_ERROR @ 26855.531573 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x406d8 read out mismatch
        UVM_INFO @ 26855.531573 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:

  • Test chip_sw_rv_core_ibex_rnd has 1 failures.

    • 1.chip_sw_rv_core_ibex_rnd.35948355907434594742992696854485147192836815562817350645133575111000731488931
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest/run.log

        UVM_ERROR @ 5505.865915 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
        UVM_INFO @ 5505.865915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = * ns has 1 failures:

  • Test chip_sw_clkmgr_off_aes_trans has 1 failures.

    • 2.chip_sw_clkmgr_off_aes_trans.30025886824332367406751389987967568863481363465506639721166558258392471156099
      Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest/run.log

        UVM_ERROR @ 12018.667439 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.667439 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36954) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 25.chip_tl_errors.99661870425223173195228475604741804121539266903574803983273749986580449022442
      Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_tl_errors/latest/run.log

        UVM_ERROR @ 4322.326396 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36954) { a_addr: 'h40550  a_data: 'hcbb36ca1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc  a_opcode: 'h4  a_user: 'h1b983  d_param: 'h0  d_source: 'hc  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 4322.326396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36416) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 27.chip_tl_errors.29975504632231025065212046300218612491320315010232588130601623116104891423990
      Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_tl_errors/latest/run.log

        UVM_ERROR @ 4114.511684 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36416) { a_addr: 'h40498  a_data: 'h394309c6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h4  a_user: 'h1b27b  d_param: 'h0  d_source: 'h37  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 4114.511684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---