AES/MASKED Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: `98165ca`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	7.000s	290.734us	1	1	100.00
V1	smoke	aes_smoke	9.000s	802.947us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	220.792us	5	5	100.00
V1	csr_rw	aes_csr_rw	2.000s	72.105us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	1.002ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	140.820us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	131.827us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	72.105us	20	20	100.00
		aes_csr_aliasing	3.000s	140.820us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	802.947us	50	50	100.00
		aes_config_error	11.000s	611.169us	50	50	100.00
		aes_stress	1.017m	4.960ms	50	50	100.00
V2	key_length	aes_smoke	9.000s	802.947us	50	50	100.00
		aes_config_error	11.000s	611.169us	50	50	100.00
		aes_stress	1.017m	4.960ms	50	50	100.00
V2	back2back	aes_stress	1.017m	4.960ms	50	50	100.00
		aes_b2b	28.000s	748.072us	50	50	100.00
V2	backpressure	aes_stress	1.017m	4.960ms	50	50	100.00
V2	multi_message	aes_smoke	9.000s	802.947us	50	50	100.00
		aes_config_error	11.000s	611.169us	50	50	100.00
		aes_stress	1.017m	4.960ms	50	50	100.00
		aes_alert_reset	9.000s	124.196us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	219.432us	50	50	100.00
		aes_config_error	11.000s	611.169us	50	50	100.00
		aes_alert_reset	9.000s	124.196us	50	50	100.00
V2	trigger_clear_test	aes_clear	11.000s	264.809us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	1.131ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	124.196us	50	50	100.00
V2	stress	aes_stress	1.017m	4.960ms	50	50	100.00
V2	sideload	aes_stress	1.017m	4.960ms	50	50	100.00
		aes_sideload	8.000s	582.758us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	573.362us	50	50	100.00
V2	stress_all	aes_stress_all	56.000s	1.618ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	69.647us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	618.829us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	618.829us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	220.792us	5	5	100.00
		aes_csr_rw	2.000s	72.105us	20	20	100.00
		aes_csr_aliasing	3.000s	140.820us	5	5	100.00
		aes_same_csr_outstanding	3.000s	79.611us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	220.792us	5	5	100.00
		aes_csr_rw	2.000s	72.105us	20	20	100.00
		aes_csr_aliasing	3.000s	140.820us	5	5	100.00
		aes_same_csr_outstanding	3.000s	79.611us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.700m	4.766ms	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	436.065us	50	50	100.00
		aes_control_fi	57.000s	10.003ms	278	300	92.67
		aes_cipher_fi	1.000m	10.102ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	119.785us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	119.785us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	119.785us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	119.785us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	379.405us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	16.000s	1.371ms	5	5	100.00
		aes_tl_intg_err	3.000s	353.029us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	353.029us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	124.196us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	119.785us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	802.947us	50	50	100.00
		aes_stress	1.017m	4.960ms	50	50	100.00
		aes_alert_reset	9.000s	124.196us	50	50	100.00
		aes_core_fi	17.000s	10.030ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	119.785us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	86.945us	50	50	100.00
		aes_stress	1.017m	4.960ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.017m	4.960ms	50	50	100.00
		aes_sideload	8.000s	582.758us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	86.945us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	86.945us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	86.945us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	86.945us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	86.945us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.017m	4.960ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.017m	4.960ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	436.065us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	436.065us	50	50	100.00
		aes_control_fi	57.000s	10.003ms	278	300	92.67
		aes_cipher_fi	1.000m	10.102ms	336	350	96.00
		aes_ctr_fi	6.000s	68.209us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	436.065us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	436.065us	50	50	100.00
		aes_control_fi	57.000s	10.003ms	278	300	92.67
		aes_cipher_fi	1.000m	10.102ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000m	10.102ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	436.065us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	436.065us	50	50	100.00
		aes_control_fi	57.000s	10.003ms	278	300	92.67
		aes_ctr_fi	6.000s	68.209us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	436.065us	50	50	100.00
		aes_control_fi	57.000s	10.003ms	278	300	92.67
		aes_cipher_fi	1.000m	10.102ms	336	350	96.00
		aes_ctr_fi	6.000s	68.209us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	124.196us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	436.065us	50	50	100.00
		aes_control_fi	57.000s	10.003ms	278	300	92.67
		aes_cipher_fi	1.000m	10.102ms	336	350	96.00
		aes_ctr_fi	6.000s	68.209us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	436.065us	50	50	100.00
		aes_control_fi	57.000s	10.003ms	278	300	92.67
		aes_cipher_fi	1.000m	10.102ms	336	350	96.00
		aes_ctr_fi	6.000s	68.209us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	436.065us	50	50	100.00
		aes_control_fi	57.000s	10.003ms	278	300	92.67
		aes_ctr_fi	6.000s	68.209us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	436.065us	50	50	100.00
		aes_control_fi	57.000s	10.003ms	278	300	92.67
		aes_cipher_fi	1.000m	10.102ms	336	350	96.00
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	27.000s	1.944ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Failure Buckets

Job timed out after * minutes has 15 failures:
- Test aes_control_fi has 14 failures.
  - 18.aes_control_fi.21748011829174246368412933844441351819470400110930774616526709781693834530155
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 25.aes_control_fi.112664005510078934089197125023480240541875737709794311238498872231539240049964
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 1 failures.
  - 334.aes_cipher_fi.74019168860362927497280234991534449870765308036960067294700395909188020878766
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/334.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 40.aes_cipher_fi.58611243424624681891332834152996270182722751679213086298651279052241094153084
    Line 135, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10025036342 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025036342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 65.aes_cipher_fi.32694737344951948284709817079559787990088627368538638386978863478393270540749
    Line 141, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/65.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007423081 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007423081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.35314757516273795033136902332220003804520323224826084329220627109195609227250
Line 601, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2573275154 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2573275154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.29957792284920570702629029143151935907308500386288949112258730228306867617917
Line 185, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  29188297 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  29188297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 24.aes_control_fi.90515309546827428993533873897019904840365040090921691594689506120346758645432
    Line 146, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011492937 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011492937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 84.aes_control_fi.98147353507604700919084136121053220285834698166560752372443764208211917486138
    Line 133, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/84.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003024920 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003024920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 4.aes_core_fi.7727048041713325750823206362173145736429808458992704611535263962495466788050
    Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030353877 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030353877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_core_fi.67048653072333270750928110938333330982550219028428694356902434734060256687914
    Line 137, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022000449 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022000449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.10264191287926931659521764780895708804273915901035487292757161820116072453591
    Line 166, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 118785896 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 118785896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.45092084553949148672297671824125720143869472779555757736962343352989716572857
    Line 202, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  82376383 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  82376383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 18.aes_clear.77702536759098346929975724537307774593947358113680391874667268805428227087247
    Line 3835, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/18.aes_clear/latest/run.log
```
  UVM_FATAL @ 166132263 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 1
           TEST FAILED MESSAGES DID NOT MATCH

                 0 6b 	 46 	 fc 	 0
                 1 18 	 a1 	 9a 	 0
```