AES/UNMASKED Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: `98165ca`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	83.087us	1	1	100.00
V1	smoke	aes_smoke	4.000s	137.974us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	95.973us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	101.659us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	2.303ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	130.471us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	70.756us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	101.659us	20	20	100.00
		aes_csr_aliasing	3.000s	130.471us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	137.974us	50	50	100.00
		aes_config_error	4.000s	229.663us	50	50	100.00
		aes_stress	4.000s	168.066us	50	50	100.00
V2	key_length	aes_smoke	4.000s	137.974us	50	50	100.00
		aes_config_error	4.000s	229.663us	50	50	100.00
		aes_stress	4.000s	168.066us	50	50	100.00
V2	back2back	aes_stress	4.000s	168.066us	50	50	100.00
		aes_b2b	6.000s	219.192us	50	50	100.00
V2	backpressure	aes_stress	4.000s	168.066us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	137.974us	50	50	100.00
		aes_config_error	4.000s	229.663us	50	50	100.00
		aes_stress	4.000s	168.066us	50	50	100.00
		aes_alert_reset	4.000s	320.662us	49	50	98.00
V2	failure_test	aes_man_cfg_err	3.000s	75.452us	50	50	100.00
		aes_config_error	4.000s	229.663us	50	50	100.00
		aes_alert_reset	4.000s	320.662us	49	50	98.00
V2	trigger_clear_test	aes_clear	4.000s	382.244us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	4.000s	190.221us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	320.662us	49	50	98.00
V2	stress	aes_stress	4.000s	168.066us	50	50	100.00
V2	sideload	aes_stress	4.000s	168.066us	50	50	100.00
		aes_sideload	3.000s	61.858us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	461.559us	50	50	100.00
V2	stress_all	aes_stress_all	17.000s	546.676us	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	123.964us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	1.394ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	1.394ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	95.973us	5	5	100.00
		aes_csr_rw	3.000s	101.659us	20	20	100.00
		aes_csr_aliasing	3.000s	130.471us	5	5	100.00
		aes_same_csr_outstanding	3.000s	284.398us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	95.973us	5	5	100.00
		aes_csr_rw	3.000s	101.659us	20	20	100.00
		aes_csr_aliasing	3.000s	130.471us	5	5	100.00
		aes_same_csr_outstanding	3.000s	284.398us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	4.000s	125.352us	50	50	100.00
V2S	fault_inject	aes_fi	3.000s	78.722us	50	50	100.00
		aes_control_fi	50.000s	200.000ms	280	300	93.33
		aes_cipher_fi	34.000s	10.008ms	333	350	95.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	252.573us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	252.573us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	252.573us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	252.573us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	1.095ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	1.634ms	5	5	100.00
		aes_tl_intg_err	4.000s	192.216us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	192.216us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	320.662us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	252.573us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	137.974us	50	50	100.00
		aes_stress	4.000s	168.066us	50	50	100.00
		aes_alert_reset	4.000s	320.662us	49	50	98.00
		aes_core_fi	37.000s	10.068ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	252.573us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	162.221us	50	50	100.00
		aes_stress	4.000s	168.066us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	168.066us	50	50	100.00
		aes_sideload	3.000s	61.858us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	162.221us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	162.221us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	162.221us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	162.221us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	162.221us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	168.066us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	168.066us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	78.722us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	78.722us	50	50	100.00
		aes_control_fi	50.000s	200.000ms	280	300	93.33
		aes_cipher_fi	34.000s	10.008ms	333	350	95.14
		aes_ctr_fi	3.000s	87.207us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	78.722us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	78.722us	50	50	100.00
		aes_control_fi	50.000s	200.000ms	280	300	93.33
		aes_cipher_fi	34.000s	10.008ms	333	350	95.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	34.000s	10.008ms	333	350	95.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	78.722us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	78.722us	50	50	100.00
		aes_control_fi	50.000s	200.000ms	280	300	93.33
		aes_ctr_fi	3.000s	87.207us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	78.722us	50	50	100.00
		aes_control_fi	50.000s	200.000ms	280	300	93.33
		aes_cipher_fi	34.000s	10.008ms	333	350	95.14
		aes_ctr_fi	3.000s	87.207us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	320.662us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	78.722us	50	50	100.00
		aes_control_fi	50.000s	200.000ms	280	300	93.33
		aes_cipher_fi	34.000s	10.008ms	333	350	95.14
		aes_ctr_fi	3.000s	87.207us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	78.722us	50	50	100.00
		aes_control_fi	50.000s	200.000ms	280	300	93.33
		aes_cipher_fi	34.000s	10.008ms	333	350	95.14
		aes_ctr_fi	3.000s	87.207us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	78.722us	50	50	100.00
		aes_control_fi	50.000s	200.000ms	280	300	93.33
		aes_ctr_fi	3.000s	87.207us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	78.722us	50	50	100.00
		aes_control_fi	50.000s	200.000ms	280	300	93.33
		aes_cipher_fi	34.000s	10.008ms	333	350	95.14
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	14.000s	4.462ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Failure Buckets

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_control_fi has 15 failures.
  - 32.aes_control_fi.13536052018786968523225988053008614400293811284431576708565484642632135767269
    Line 149, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002955270 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002955270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 69.aes_control_fi.97525662151377218027430680423936876719199081580151139936561578259836072600543
    Line 146, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/69.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005159373 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005159373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.
Job timed out after * minutes has 13 failures:
- Test aes_cipher_fi has 9 failures.
  - 6.aes_cipher_fi.76593635680597947225469576289223348778296798184085892269409155173740170114972
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 26.aes_cipher_fi.86680264139111636026005567323879820344447699046977132572347948211057160092873
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
- Test aes_control_fi has 4 failures.
  - 19.aes_control_fi.25488791569288730470587465493719379582749552118800351048398442255732312237646
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 40.aes_control_fi.12292531261888206326718433959686926881619323461383655504199913072599049262227
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 5.aes_cipher_fi.33689239590535385981822245600299200539781497555091472613007671695340096805165
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006472290 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006472290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 104.aes_cipher_fi.26699160973823950942975087048213427591154292881330661794340524393439065189225
    Line 148, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/104.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006071157 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006071157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.93270196635476133267178517954007060648055237422163978527361166866275322219301
Line 763, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 258691506 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 258691506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.21744852309420702574534566917870281945041652020445557842396459485202028746182
Line 664, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1072985381 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1072985381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 6.aes_stress_all_with_rand_reset.10519867833403669236569330396149853276648706189647769621344546275383810237386
    Line 244, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4462258981 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 4462258981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.88289279645423558393755071087172088732159715125933585630151361938080375929530
    Line 454, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 160288516 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 160288516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.91443861307271807864872196437925246245383744493610588265290225490035174020212
    Line 360, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 492033901 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 492033901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block.status reset value: * has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.100925336802046908944911400835595801225839812894782624343837086813764256442670
    Line 171, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1283723667 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (64 [0x40] vs 0 [0x0]) Regname: aes_reg_block.status reset value: 0x0
  UVM_INFO @ 1283723667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 29.aes_alert_reset.106098128068878537526837610216751157190765793991928681953709440673661216323818
    Line 3133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/29.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 11865954 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 11855954 PS)
  UVM_ERROR @  11865954 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  11865954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 38.aes_core_fi.103034581834466349377577125883794051474634657854743827196726989608261873644352
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10068110895 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xf64c1584, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10068110895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 90.aes_control_fi.109422955155876150358146409593397885766778794325400822804474619551650988092413
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/90.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```