AON_TIMER Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.910s	535.101us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.340s	1.123ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.610s	334.654us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	14.800s	7.126ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.660s	624.545us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.960s	519.695us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.610s	334.654us	20	20	100.00
		aon_timer_csr_aliasing	1.660s	624.545us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.400s	427.546us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.830s	397.879us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	1.264m	53.565ms	15	15	100.00
V2	jump	aon_timer_jump	1.500s	572.307us	5	5	100.00
V2	stress_all	aon_timer_stress_all	2.399m	109.146ms	15	15	100.00
V2	alert_test	aon_timer_alert_test	1.990s	490.980us	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.670s	495.312us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.900s	550.629us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.900s	550.629us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.340s	1.123ms	5	5	100.00
		aon_timer_csr_rw	1.610s	334.654us	20	20	100.00
		aon_timer_csr_aliasing	1.660s	624.545us	5	5	100.00
		aon_timer_same_csr_outstanding	6.600s	2.932ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.340s	1.123ms	5	5	100.00
		aon_timer_csr_rw	1.610s	334.654us	20	20	100.00
		aon_timer_csr_aliasing	1.660s	624.545us	5	5	100.00
		aon_timer_same_csr_outstanding	6.600s	2.932ms	20	20	100.00
V2		TOTAL			175	175	100.00
V2S	tl_intg_err	aon_timer_sec_cm	10.680s	7.792ms	5	5	100.00
		aon_timer_tl_intg_err	16.410s	7.956ms	19	20	95.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	16.410s	7.956ms	19	20	95.00
V2S		TOTAL			24	25	96.00
V3	max_threshold	aon_timer_smoke_max_thold	1.240s	656.677us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	1.420s	552.592us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	9.680s	4.145ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	2.170s	665.192us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	15.920s	4.158ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	36.230s	53.444ms	15	15	100.00
V3		TOTAL			45	45	100.00
		TOTAL			314	315	99.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [aon_timer_common_vseq] expect alert:fatal_fault to fire has 1 failures:
  • Test aon_timer_tl_intg_err has 1 failures.

    • 6.aon_timer_tl_intg_err.28373187389900293294945149155972338354768778434566433279244603131533832948542
      Line 102, in log /nightly/current_run/scratch/master/aon_timer-sim-vcs/6.aon_timer_tl_intg_err/latest/run.log

        UVM_ERROR @ 1768355081 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] expect alert:fatal_fault to fire
        UVM_INFO @ 1768355081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---