DMA Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	9.000s	1.288ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	11.000s	683.184us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	9.000s	694.466us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	71.359us	5	5	100.00
V1	csr_rw	dma_csr_rw	2.000s	99.567us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	11.000s	3.806ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	302.562us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	3.000s	80.729us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	99.567us	20	20	100.00
		dma_csr_aliasing	7.000s	302.562us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.200m	7.532ms	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	4.433m	139.935ms	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	8.467m	396.675ms	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	8.467m	396.675ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	4.433m	139.935ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	19.617m	105.280ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	8.467m	396.675ms	3	3	100.00
V2	dma_abort	dma_abort	13.000s	830.659us	5	5	100.00
V2	dma_stress_all	dma_stress_all	2.800m	54.959ms	3	3	100.00
V2	alert_test	dma_alert_test	2.000s	17.379us	50	50	100.00
V2	intr_test	dma_intr_test	4.000s	12.932us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	1.908ms	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	1.908ms	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	71.359us	5	5	100.00
		dma_csr_rw	2.000s	99.567us	20	20	100.00
		dma_csr_aliasing	7.000s	302.562us	5	5	100.00
		dma_same_csr_outstanding	3.000s	96.782us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	71.359us	5	5	100.00
		dma_csr_rw	2.000s	99.567us	20	20	100.00
		dma_csr_aliasing	7.000s	302.562us	5	5	100.00
		dma_same_csr_outstanding	3.000s	96.782us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	19.000s	266.038us	5	5	100.00
		dma_generic_stress	19.617m	105.280ms	5	5	100.00
		dma_handshake_stress	8.467m	396.675ms	3	3	100.00
V2S	dma_config_lock	dma_config_lock	10.000s	572.571us	15	15	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	1.005ms	20	20	100.00
		dma_sec_cm	2.000s	33.919us	5	5	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	2.717m	56.759ms	25	25	100.00
		dma_longer_transfer	18.000s	5.000ms	5	5	100.00
		dma_stress_all_with_rand_reset	13.000s	628.237us	0	1	0.00
		TOTAL			394	395	99.75

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.96474065264336996978603259807447173273227447832586654423471589473245720670552
      Line 105, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  628236650ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  628236650ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---