EDN Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.460s	24.201us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.900s	16.629us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.010s	26.059us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.380s	513.429us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.200s	117.506us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.390s	34.505us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.010s	26.059us	20	20	100.00
		edn_csr_aliasing	1.200s	117.506us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	52.800s	2.261ms	300	300	100.00
V2	csrng_commands	edn_genbits	52.800s	2.261ms	300	300	100.00
V2	genbits	edn_genbits	52.800s	2.261ms	300	300	100.00
V2	interrupts	edn_intr	1.470s	21.500us	50	50	100.00
V2	alerts	edn_alert	1.520s	34.965us	200	200	100.00
V2	errs	edn_err	1.460s	86.155us	100	100	100.00
V2	disable	edn_disable	1.210s	20.443us	50	50	100.00
		edn_disable_auto_req_mode	1.760s	70.570us	50	50	100.00
V2	stress_all	edn_stress_all	5.870s	555.290us	50	50	100.00
V2	intr_test	edn_intr_test	0.980s	17.531us	50	50	100.00
V2	alert_test	edn_alert_test	1.180s	34.890us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.130s	467.619us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.130s	467.619us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.900s	16.629us	5	5	100.00
		edn_csr_rw	1.010s	26.059us	20	20	100.00
		edn_csr_aliasing	1.200s	117.506us	5	5	100.00
		edn_same_csr_outstanding	1.310s	37.569us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.900s	16.629us	5	5	100.00
		edn_csr_rw	1.010s	26.059us	20	20	100.00
		edn_csr_aliasing	1.200s	117.506us	5	5	100.00
		edn_same_csr_outstanding	1.310s	37.569us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	7.030s	6.082ms	5	5	100.00
		edn_tl_intg_err	6.120s	2.200ms	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.980s	27.016us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.520s	34.965us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.030s	6.082ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.030s	6.082ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.030s	6.082ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.030s	6.082ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.520s	34.965us	200	200	100.00
		edn_sec_cm	7.030s	6.082ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.520s	34.965us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	6.120s	2.200ms	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.610m	21.171ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1113	1130	98.50

Failure Buckets

• Job timed out after * minutes has 16 failures:
  • Test edn_stress_all_with_rand_reset has 16 failures.

    • 1.edn_stress_all_with_rand_reset.10252213388346045260176865872536974816497323265682298948647094078408771791991
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 4.edn_stress_all_with_rand_reset.110994274719640906683623953633258758716966061972583013108868797742420764614635
      Log /nightly/current_run/scratch/master/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 14 more failures.

• UVM_ERROR (cip_base_vseq.sv:1142) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 7.edn_stress_all_with_rand_reset.16310581199911514874635338981344618861362298704983173860676067010352490322989
      Line 224, in log /nightly/current_run/scratch/master/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1247623659 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1247623659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---