HMAC Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 14.420s 1.133ms 10 10 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.270s 39.899us 5 5 100.00
V1 csr_rw hmac_csr_rw 1.280s 19.148us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 12.880s 6.503ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 8.000s 449.383us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 10.553m 230.430ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.280s 19.148us 20 20 100.00
hmac_csr_aliasing 8.000s 449.383us 5 5 100.00
V1 TOTAL 65 65 100.00
V2 long_msg hmac_long_msg 1.081m 1.475ms 10 10 100.00
V2 back_pressure hmac_back_pressure 1.417m 3.270ms 25 25 100.00
V2 test_vectors hmac_test_sha256_vectors 4.199m 6.755ms 30 30 100.00
hmac_test_sha384_vectors 8.737m 66.134ms 75 75 100.00
hmac_test_sha512_vectors 9.031m 14.696ms 75 75 100.00
hmac_test_hmac256_vectors 14.610s 342.520us 50 50 100.00
hmac_test_hmac384_vectors 16.450s 7.555ms 60 60 100.00
hmac_test_hmac512_vectors 18.330s 392.423us 75 75 100.00
V2 burst_wr hmac_burst_wr 45.220s 2.683ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 23.040m 8.279ms 10 10 100.00
V2 error hmac_error 1.510m 25.468ms 10 10 100.00
V2 wipe_secret hmac_wipe_secret 1.191m 5.433ms 10 10 100.00
V2 save_and_restore hmac_smoke 14.420s 1.133ms 10 10 100.00
hmac_long_msg 1.081m 1.475ms 10 10 100.00
hmac_back_pressure 1.417m 3.270ms 25 25 100.00
hmac_datapath_stress 23.040m 8.279ms 10 10 100.00
hmac_burst_wr 45.220s 2.683ms 50 50 100.00
hmac_stress_all 39.525m 82.712ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 14.420s 1.133ms 10 10 100.00
hmac_long_msg 1.081m 1.475ms 10 10 100.00
hmac_back_pressure 1.417m 3.270ms 25 25 100.00
hmac_datapath_stress 23.040m 8.279ms 10 10 100.00
hmac_wipe_secret 1.191m 5.433ms 10 10 100.00
hmac_test_sha256_vectors 4.199m 6.755ms 30 30 100.00
hmac_test_sha384_vectors 8.737m 66.134ms 75 75 100.00
hmac_test_sha512_vectors 9.031m 14.696ms 75 75 100.00
hmac_test_hmac256_vectors 14.610s 342.520us 50 50 100.00
hmac_test_hmac384_vectors 16.450s 7.555ms 60 60 100.00
hmac_test_hmac512_vectors 18.330s 392.423us 75 75 100.00
V2 wide_digest_configurable_key_length hmac_smoke 14.420s 1.133ms 10 10 100.00
hmac_long_msg 1.081m 1.475ms 10 10 100.00
hmac_back_pressure 1.417m 3.270ms 25 25 100.00
hmac_datapath_stress 23.040m 8.279ms 10 10 100.00
hmac_burst_wr 45.220s 2.683ms 50 50 100.00
hmac_error 1.510m 25.468ms 10 10 100.00
hmac_wipe_secret 1.191m 5.433ms 10 10 100.00
hmac_test_sha256_vectors 4.199m 6.755ms 30 30 100.00
hmac_test_sha384_vectors 8.737m 66.134ms 75 75 100.00
hmac_test_sha512_vectors 9.031m 14.696ms 75 75 100.00
hmac_test_hmac256_vectors 14.610s 342.520us 50 50 100.00
hmac_test_hmac384_vectors 16.450s 7.555ms 60 60 100.00
hmac_test_hmac512_vectors 18.330s 392.423us 75 75 100.00
hmac_stress_all 39.525m 82.712ms 50 50 100.00
V2 stress_all hmac_stress_all 39.525m 82.712ms 50 50 100.00
V2 alert_test hmac_alert_test 0.960s 13.540us 50 50 100.00
V2 intr_test hmac_intr_test 0.970s 12.944us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.420s 428.643us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.420s 428.643us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.270s 39.899us 5 5 100.00
hmac_csr_rw 1.280s 19.148us 20 20 100.00
hmac_csr_aliasing 8.000s 449.383us 5 5 100.00
hmac_same_csr_outstanding 2.790s 421.654us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.270s 39.899us 5 5 100.00
hmac_csr_rw 1.280s 19.148us 20 20 100.00
hmac_csr_aliasing 8.000s 449.383us 5 5 100.00
hmac_same_csr_outstanding 2.790s 421.654us 20 20 100.00
V2 TOTAL 670 670 100.00
V2S tl_intg_err hmac_sec_cm 1.470s 223.379us 5 5 100.00
hmac_tl_intg_err 4.970s 1.094ms 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.970s 1.094ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 14.420s 1.133ms 10 10 100.00
V3 stress_reset hmac_stress_reset 7.810s 286.269us 25 25 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 6.424m 64.882ms 35 35 100.00
V3 TOTAL 60 60 100.00
Unmapped tests hmac_directed 2.730s 37.628us 1 1 100.00
TOTAL 821 821 100.00