KEYMGR Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	24.540s	3.079ms	50	50	100.00
V1	random	keymgr_random	38.820s	1.588ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.610s	71.011us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.650s	225.601us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	18.860s	1.918ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.460s	725.510us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.210s	233.859us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.650s	225.601us	20	20	100.00
		keymgr_csr_aliasing	7.460s	725.510us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.828m	10.322ms	50	50	100.00
V2	sideload	keymgr_sideload	38.420s	1.592ms	50	50	100.00
		keymgr_sideload_kmac	51.970s	6.572ms	50	50	100.00
		keymgr_sideload_aes	22.760s	3.649ms	49	50	98.00
		keymgr_sideload_otbn	37.450s	4.771ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	16.620s	656.730us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	13.020s	10.095ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	8.580s	477.986us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	47.670s	1.904ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	34.250s	5.713ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	14.890s	1.428ms	50	50	100.00
V2	stress_all	keymgr_stress_all	2.988m	21.284ms	49	50	98.00
V2	intr_test	keymgr_intr_test	1.250s	18.126us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.370s	62.377us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.220s	223.217us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.220s	223.217us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.610s	71.011us	5	5	100.00
		keymgr_csr_rw	1.650s	225.601us	20	20	100.00
		keymgr_csr_aliasing	7.460s	725.510us	5	5	100.00
		keymgr_same_csr_outstanding	3.600s	97.268us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.610s	71.011us	5	5	100.00
		keymgr_csr_rw	1.650s	225.601us	20	20	100.00
		keymgr_csr_aliasing	7.460s	725.510us	5	5	100.00
		keymgr_same_csr_outstanding	3.600s	97.268us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	tl_intg_err	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
		keymgr_tl_intg_err	7.400s	233.066us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.040s	690.801us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.040s	690.801us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.040s	690.801us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.040s	690.801us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.150s	3.328ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	prim_fsm_check	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.400s	233.066us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.040s	690.801us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.828m	10.322ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	38.820s	1.588ms	50	50	100.00
		keymgr_csr_rw	1.650s	225.601us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	38.820s	1.588ms	50	50	100.00
		keymgr_csr_rw	1.650s	225.601us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	38.820s	1.588ms	50	50	100.00
		keymgr_csr_rw	1.650s	225.601us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	13.020s	10.095ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	34.250s	5.713ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	34.250s	5.713ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	38.820s	1.588ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	40.020s	10.933ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	30.410s	3.371ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	13.020s	10.095ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	30.410s	3.371ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	30.410s	3.371ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	30.410s	3.371ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.850s	968.830us	4	5	80.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	30.410s	3.371ms	50	50	100.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	24.290s	2.079ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1078	1110	97.12

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test keymgr_stress_all_with_rand_reset has 27 failures.

    • 0.keymgr_stress_all_with_rand_reset.102226049910124424460944051697070469535294550233684097985334740472892771376814
      Line 306, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 745248372 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 745248372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.keymgr_stress_all_with_rand_reset.102193186848588627325189060544848231466853045799554511422241733789843813683630
      Line 600, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 444701419 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 444701419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_stress_all has 1 failures.

    • 6.keymgr_stress_all.111051513967626694267671743592075342958354506025941155132319251300343640014397
      Line 2460, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 1190152303 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 1190152303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload_aes has 1 failures.

    • 25.keymgr_sideload_aes.32202640910698524044560904097472713151309785102293584313713823580341671049259
      Line 108, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_sideload_aes/latest/run.log

        UVM_ERROR @   4111620 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @   4111620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [keymgr_common_vseq] expect alert:fatal_fault_err to fire has 1 failures:

  • Test keymgr_sec_cm has 1 failures.

    • 3.keymgr_sec_cm.17762589267726308239912593234861504502634792305621712104311182398579547587567
      Line 796, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_sec_cm/latest/run.log

        UVM_ERROR @ 687824800 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] expect alert:fatal_fault_err to fire
        UVM_INFO @ 687824800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout keymgr_reg_block.working_state (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test keymgr_lc_disable has 1 failures.

    • 39.keymgr_lc_disable.70330904960811586106556874778610743858881156939454137577156676071503976422985
      Line 229, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/39.keymgr_lc_disable/latest/run.log

        UVM_FATAL @ 10095017095 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout keymgr_reg_block.working_state (addr=0xd82eede8, Comparison=CompareOpEq, exp_data=0x4, call_count=2)
        UVM_INFO @ 10095017095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:

  • Test keymgr_hwsw_invalid_input has 1 failures.

    • 47.keymgr_hwsw_invalid_input.7365164025645004402633919795054454807955750868568369044327950730329095040673
      Line 324, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest/run.log

        UVM_ERROR @  21087946 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  21087946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---