KEYMGR_DPE Simulation Results

Friday November 07 2025 17:06:22 UTC

GitHub Revision: 98165ca

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	5.832m	101.607ms	50	50	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.710s	29.426us	4	5	80.00
V1	csr_rw	keymgr_dpe_csr_rw	1.670s	24.080us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	8.800s	341.467us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	7.410s	889.241us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.250s	91.235us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.670s	24.080us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.410s	889.241us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	intr_test	keymgr_dpe_intr_test	1.140s	28.233us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.350s	16.445us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.410s	137.746us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.410s	137.746us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.710s	29.426us	4	5	80.00
		keymgr_dpe_csr_rw	1.670s	24.080us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.410s	889.241us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.010s	551.320us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.710s	29.426us	4	5	80.00
		keymgr_dpe_csr_rw	1.670s	24.080us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.410s	889.241us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.010s	551.320us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	13.200s	3.738ms	5	5	100.00
		keymgr_dpe_tl_intg_err	6.580s	1.032ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.440s	124.891us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.440s	124.891us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.440s	124.891us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.440s	124.891us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	7.740s	450.958us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	13.200s	3.738ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	13.200s	3.738ms	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			309	310	99.68

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: * has 1 failures:
  • Test keymgr_dpe_csr_hw_reset has 1 failures.

    • 4.keymgr_dpe_csr_hw_reset.71284157988775546813805370968199013861888512508657928001306165326380537289013
      Line 85, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/4.keymgr_dpe_csr_hw_reset/latest/run.log

        UVM_ERROR @  24358918 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
        UVM_INFO @  24358918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---